intel/isl: Add a helper for composing swizzles

[mesa.git] / src / intel / isl / isl_gen9.c

diff --git a/src/intel/isl/isl_gen9.c b/src/intel/isl/isl_gen9.c
index ff0dec955a58e14d87e0b9ff4c21856d5a43116e..e5d0f95402a4ef82d9d1c2d76d9ba85bf86eb784 100644 (file)
--- a/src/intel/isl/isl_gen9.c
+++ b/src/intel/isl/isl_gen9.c
@@ -97,15 +97,28 @@ gen9_calc_std_image_alignment_sa(const struct isl_device *dev,
 }
 
 void
-gen9_choose_image_alignment_el(const struct isl_device *dev,
-                               const struct isl_surf_init_info *restrict info,
-                               enum isl_tiling tiling,
-                               enum isl_msaa_layout msaa_layout,
-                               struct isl_extent3d *image_align_el)
+isl_gen9_choose_image_alignment_el(const struct isl_device *dev,
+                                   const struct isl_surf_init_info *restrict info,
+                                   enum isl_tiling tiling,
+                                   enum isl_dim_layout dim_layout,
+                                   enum isl_msaa_layout msaa_layout,
+                                   struct isl_extent3d *image_align_el)
 {
    /* Handled by isl_choose_image_alignment_el */
    assert(info->format != ISL_FORMAT_HIZ);
 
+   const struct isl_format_layout *fmtl = isl_format_get_layout(info->format);
+   if (fmtl->txc == ISL_TXC_CCS) {
+      /* Sky Lake PRM Vol. 7, "MCS Buffer for Render Target(s)" (p. 632):
+       *
+       *    "Mip-mapped and arrayed surfaces are supported with MCS buffer
+       *    layout with these alignments in the RT space: Horizontal
+       *    Alignment = 128 and Vertical Alignment = 64."
+       */
+      *image_align_el = isl_extent3d(128 / fmtl->bw, 64 / fmtl->bh, 1);
+      return;
+   }
+
    /* This BSpec text provides some insight into the hardware's alignment
     * requirements [Skylake BSpec > Memory Views > Common Surface Formats >
     * Surface Layout and Tiling > 2D Surfaces]:
@@ -161,7 +174,7 @@ gen9_choose_image_alignment_el(const struct isl_device *dev,
       return;
    }
 
-   if (info->dim == ISL_SURF_DIM_1D) {
+   if (dim_layout == ISL_DIM_LAYOUT_GEN9_1D) {
       /* See the Skylake BSpec > Memory Views > Common Surface Formats > Surface
        * Layout and Tiling > 1D Surfaces > 1D Alignment Requirements.
        */
@@ -183,6 +196,6 @@ gen9_choose_image_alignment_el(const struct isl_device *dev,
       return;
    }
 
-   gen8_choose_image_alignment_el(dev, info, tiling, msaa_layout,
-                                  image_align_el);
+   isl_gen8_choose_image_alignment_el(dev, info, tiling, dim_layout,
+                                      msaa_layout, image_align_el);
 }