intel/isl: Add a unit suffixes to some struct fields and variables

[mesa.git] / src / intel / isl / isl_surface_state.c

diff --git a/src/intel/isl/isl_surface_state.c b/src/intel/isl/isl_surface_state.c
index bff9693f02d676f6accdf8bd332511dbd43c60aa..7ab260d701b294393243895d35a106edc7621d45 100644 (file)
--- a/src/intel/isl/isl_surface_state.c
+++ b/src/intel/isl/isl_surface_state.c
@@ -430,7 +430,7 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state,
       /* For gen9 1-D textures, surface pitch is ignored */
       s.SurfacePitch = 0;
    } else {
-      s.SurfacePitch = info->surf->row_pitch - 1;
+      s.SurfacePitch = info->surf->row_pitch_B - 1;
    }
 
 #if GEN_GEN >= 8
@@ -470,42 +470,15 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state,
 #endif
 
 #if (GEN_GEN >= 8 || GEN_IS_HASWELL)
-   if (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) {
-      /* From the Sky Lake PRM Vol. 2d,
-       * RENDER_SURFACE_STATE::Shader Channel Select Red
-       *
-       *    "For Render Target, Red, Green and Blue Shader Channel Selects
-       *    MUST be such that only valid components can be swapped i.e. only
-       *    change the order of components in the pixel. Any other values for
-       *    these Shader Channel Select fields are not valid for Render
-       *    Targets. This also means that there MUST not be multiple shader
-       *    channels mapped to the same RT channel."
-       */
-      assert(info->view->swizzle.r == ISL_CHANNEL_SELECT_RED ||
-             info->view->swizzle.r == ISL_CHANNEL_SELECT_GREEN ||
-             info->view->swizzle.r == ISL_CHANNEL_SELECT_BLUE);
-      assert(info->view->swizzle.g == ISL_CHANNEL_SELECT_RED ||
-             info->view->swizzle.g == ISL_CHANNEL_SELECT_GREEN ||
-             info->view->swizzle.g == ISL_CHANNEL_SELECT_BLUE);
-      assert(info->view->swizzle.b == ISL_CHANNEL_SELECT_RED ||
-             info->view->swizzle.b == ISL_CHANNEL_SELECT_GREEN ||
-             info->view->swizzle.b == ISL_CHANNEL_SELECT_BLUE);
-      assert(info->view->swizzle.r != info->view->swizzle.g);
-      assert(info->view->swizzle.r != info->view->swizzle.b);
-      assert(info->view->swizzle.g != info->view->swizzle.b);
-
-      /* From the Sky Lake PRM Vol. 2d,
-       * RENDER_SURFACE_STATE::Shader Channel Select Alpha
-       *
-       *    "For Render Target, this field MUST be programmed to
-       *    value = SCS_ALPHA."
-       */
-      assert(info->view->swizzle.a == ISL_CHANNEL_SELECT_ALPHA);
-   }
+   if (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT)
+      assert(isl_swizzle_supports_rendering(dev->info, info->view->swizzle));
+
    s.ShaderChannelSelectRed = (enum GENX(ShaderChannelSelect)) info->view->swizzle.r;
    s.ShaderChannelSelectGreen = (enum GENX(ShaderChannelSelect)) info->view->swizzle.g;
    s.ShaderChannelSelectBlue = (enum GENX(ShaderChannelSelect)) info->view->swizzle.b;
    s.ShaderChannelSelectAlpha = (enum GENX(ShaderChannelSelect)) info->view->swizzle.a;
+#else
+   assert(isl_swizzle_is_identity(info->view->swizzle));
 #endif
 
    s.SurfaceBaseAddress = info->address;
@@ -563,7 +536,7 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state,
       struct isl_tile_info tile_info;
       isl_surf_get_tile_info(info->aux_surf, &tile_info);
       uint32_t pitch_in_tiles =
-         info->aux_surf->row_pitch / tile_info.phys_extent_B.width;
+         info->aux_surf->row_pitch_B / tile_info.phys_extent_B.width;
 
       s.AuxiliarySurfaceBaseAddress = info->aux_address;
       s.AuxiliarySurfacePitch = pitch_in_tiles - 1;
@@ -685,7 +658,7 @@ void
 isl_genX(buffer_fill_state_s)(void *state,
                               const struct isl_buffer_fill_state_info *restrict info)
 {
-   uint64_t buffer_size = info->size;
+   uint64_t buffer_size = info->size_B;
 
    /* Uniform and Storage buffers need to have surface size not less that the
     * aligned 32-bit size of the buffer. To calculate the array lenght on
@@ -699,13 +672,13 @@ isl_genX(buffer_fill_state_s)(void *state,
     *  buffer_size = (surface_size & ~3) - (surface_size & 3)
     */
    if (info->format == ISL_FORMAT_RAW  ||
-       info->stride < isl_format_get_layout(info->format)->bpb / 8) {
-      assert(info->stride == 1);
+       info->stride_B < isl_format_get_layout(info->format)->bpb / 8) {
+      assert(info->stride_B == 1);
       uint64_t aligned_size = isl_align(buffer_size, 4);
       buffer_size = aligned_size + (aligned_size - buffer_size);
    }
 
-   uint32_t num_elements = buffer_size / info->stride;
+   uint32_t num_elements = buffer_size / info->stride_B;
 
    if (GEN_GEN >= 7) {
       /* From the IVB PRM, SURFACE_STATE::Height,
@@ -748,7 +721,7 @@ isl_genX(buffer_fill_state_s)(void *state,
    s.Depth = ((num_elements - 1) >> 20) & 0x7f;
 #endif
 
-   s.SurfacePitch = info->stride - 1;
+   s.SurfacePitch = info->stride_B - 1;
 
 #if GEN_GEN >= 6
    s.NumberofMultisamples = MULTISAMPLECOUNT_1;