#define __gen_user_data void
static uint64_t
-__gen_combine_address(void *data, void *loc, uint64_t addr, uint32_t delta)
+__gen_combine_address(__attribute__((unused)) void *data,
+ __attribute__((unused)) void *loc, uint64_t addr,
+ uint32_t delta)
{
return addr + delta;
}
[ISL_TILING_Y0] = YMAJOR,
[ISL_TILING_Yf] = YMAJOR,
[ISL_TILING_Ys] = YMAJOR,
+#if GEN_GEN <= 11
[ISL_TILING_W] = WMAJOR,
+#endif
};
#endif
};
#endif
-#if GEN_GEN >= 9
+#if GEN_GEN >= 12
+static const uint32_t isl_to_gen_aux_mode[] = {
+ [ISL_AUX_USAGE_NONE] = AUX_NONE,
+ [ISL_AUX_USAGE_MCS] = AUX_CCS_E,
+ [ISL_AUX_USAGE_CCS_E] = AUX_CCS_E,
+ [ISL_AUX_USAGE_MCS_CCS] = AUX_MCS_LCE,
+};
+#elif GEN_GEN >= 9
static const uint32_t isl_to_gen_aux_mode[] = {
[ISL_AUX_USAGE_NONE] = AUX_NONE,
[ISL_AUX_USAGE_HIZ] = AUX_HIZ,
* S3TC workaround that requires us to do reinterpretation. So assert
* that they're at least the same bpb and block size.
*/
- MAYBE_UNUSED const struct isl_format_layout *surf_fmtl =
+ ASSERTED const struct isl_format_layout *surf_fmtl =
isl_format_get_layout(info->surf->format);
- MAYBE_UNUSED const struct isl_format_layout *view_fmtl =
+ ASSERTED const struct isl_format_layout *view_fmtl =
isl_format_get_layout(info->surf->format);
assert(surf_fmtl->bpb == view_fmtl->bpb);
assert(surf_fmtl->bw == view_fmtl->bw);
assert(surf_fmtl->bh == view_fmtl->bh);
}
- s.SurfaceFormat = (enum GENX(SURFACE_FORMAT)) info->view->format;
+ s.SurfaceFormat = info->view->format;
+
+#if GEN_GEN >= 12
+ s.DepthStencilResource =
+ isl_surf_usage_is_depth_or_stencil(info->surf->usage);
+#endif
#if GEN_GEN <= 5
s.ColorBufferComponentWriteDisables = info->write_disables;
unreachable("bad SurfaceType");
}
-#if GEN_GEN >= 7
+#if GEN_GEN >= 12
+ /* GEN:BUG:1806565034: Only set SurfaceArray if arrayed surface is > 1. */
+ s.SurfaceArray = info->surf->dim != ISL_SURF_DIM_3D &&
+ info->view->array_len > 1;
+#elif GEN_GEN >= 7
s.SurfaceArray = info->surf->dim != ISL_SURF_DIM_3D;
#endif
/* For gen9 1-D textures, surface pitch is ignored */
s.SurfacePitch = 0;
} else {
- s.SurfacePitch = info->surf->row_pitch - 1;
+ s.SurfacePitch = info->surf->row_pitch_B - 1;
}
#if GEN_GEN >= 8
#endif
#if GEN_GEN >= 8
+ assert(GEN_GEN < 12 || info->surf->tiling != ISL_TILING_W);
s.TileMode = isl_to_gen_tiling[info->surf->tiling];
#else
s.TiledSurface = info->surf->tiling != ISL_TILING_LINEAR,
s.RenderCacheReadWriteMode = 0;
#endif
- if (info->view->usage & ISL_SURF_USAGE_CUBE_BIT) {
- s.CubeFaceEnablePositiveZ = 1;
- s.CubeFaceEnableNegativeZ = 1;
- s.CubeFaceEnablePositiveY = 1;
- s.CubeFaceEnableNegativeY = 1;
- s.CubeFaceEnablePositiveX = 1;
- s.CubeFaceEnableNegativeX = 1;
- }
+#if GEN_GEN >= 11
+ /* We've seen dEQP failures when enabling this bit with UINT formats,
+ * which particularly affects blorp_copy() operations. It shouldn't
+ * have any effect on UINT textures anyway, so disable it for them.
+ */
+ s.EnableUnormPathInColorPipe =
+ !isl_format_has_int_channel(info->view->format);
+#endif
+
+ s.CubeFaceEnablePositiveZ = 1;
+ s.CubeFaceEnableNegativeZ = 1;
+ s.CubeFaceEnablePositiveY = 1;
+ s.CubeFaceEnableNegativeY = 1;
+ s.CubeFaceEnablePositiveX = 1;
+ s.CubeFaceEnableNegativeX = 1;
#if GEN_GEN >= 6
s.NumberofMultisamples = ffs(info->surf->samples) - 1;
#endif
#if (GEN_GEN >= 8 || GEN_IS_HASWELL)
- if (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) {
- /* From the Sky Lake PRM Vol. 2d,
- * RENDER_SURFACE_STATE::Shader Channel Select Red
- *
- * "For Render Target, Red, Green and Blue Shader Channel Selects
- * MUST be such that only valid components can be swapped i.e. only
- * change the order of components in the pixel. Any other values for
- * these Shader Channel Select fields are not valid for Render
- * Targets. This also means that there MUST not be multiple shader
- * channels mapped to the same RT channel."
- */
- assert(info->view->swizzle.r == ISL_CHANNEL_SELECT_RED ||
- info->view->swizzle.r == ISL_CHANNEL_SELECT_GREEN ||
- info->view->swizzle.r == ISL_CHANNEL_SELECT_BLUE);
- assert(info->view->swizzle.g == ISL_CHANNEL_SELECT_RED ||
- info->view->swizzle.g == ISL_CHANNEL_SELECT_GREEN ||
- info->view->swizzle.g == ISL_CHANNEL_SELECT_BLUE);
- assert(info->view->swizzle.b == ISL_CHANNEL_SELECT_RED ||
- info->view->swizzle.b == ISL_CHANNEL_SELECT_GREEN ||
- info->view->swizzle.b == ISL_CHANNEL_SELECT_BLUE);
- assert(info->view->swizzle.r != info->view->swizzle.g);
- assert(info->view->swizzle.r != info->view->swizzle.b);
- assert(info->view->swizzle.g != info->view->swizzle.b);
-
- /* From the Sky Lake PRM Vol. 2d,
- * RENDER_SURFACE_STATE::Shader Channel Select Alpha
- *
- * "For Render Target, this field MUST be programmed to
- * value = SCS_ALPHA."
- */
- assert(info->view->swizzle.a == ISL_CHANNEL_SELECT_ALPHA);
- }
+ if (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT)
+ assert(isl_swizzle_supports_rendering(dev->info, info->view->swizzle));
+
s.ShaderChannelSelectRed = (enum GENX(ShaderChannelSelect)) info->view->swizzle.r;
s.ShaderChannelSelectGreen = (enum GENX(ShaderChannelSelect)) info->view->swizzle.g;
s.ShaderChannelSelectBlue = (enum GENX(ShaderChannelSelect)) info->view->swizzle.b;
s.ShaderChannelSelectAlpha = (enum GENX(ShaderChannelSelect)) info->view->swizzle.a;
+#else
+ assert(isl_swizzle_is_identity(info->view->swizzle));
#endif
s.SurfaceBaseAddress = info->address;
#endif
#if GEN_GEN >= 7
- if (info->aux_surf && info->aux_usage != ISL_AUX_USAGE_NONE) {
+ if (info->aux_usage != ISL_AUX_USAGE_NONE) {
+ /* Check valid aux usages per-gen */
+ if (GEN_GEN >= 12) {
+ assert(info->aux_usage == ISL_AUX_USAGE_MCS ||
+ info->aux_usage == ISL_AUX_USAGE_CCS_E ||
+ info->aux_usage == ISL_AUX_USAGE_MCS_CCS);
+ } else if (GEN_GEN >= 9) {
+ assert(info->aux_usage == ISL_AUX_USAGE_HIZ ||
+ info->aux_usage == ISL_AUX_USAGE_MCS ||
+ info->aux_usage == ISL_AUX_USAGE_CCS_D ||
+ info->aux_usage == ISL_AUX_USAGE_CCS_E);
+ } else if (GEN_GEN >= 8) {
+ assert(info->aux_usage == ISL_AUX_USAGE_HIZ ||
+ info->aux_usage == ISL_AUX_USAGE_MCS ||
+ info->aux_usage == ISL_AUX_USAGE_CCS_D);
+ } else if (GEN_GEN >= 7) {
+ assert(info->aux_usage == ISL_AUX_USAGE_MCS ||
+ info->aux_usage == ISL_AUX_USAGE_CCS_D);
+ }
+
+ if (GEN_GEN >= 12) {
+ /* We don't need an auxiliary surface for CCS on gen12+ */
+ assert (info->aux_usage == ISL_AUX_USAGE_CCS_E ||
+ info->aux_usage == ISL_AUX_USAGE_MC || info->aux_surf);
+ } else {
+ /* We must have an auxiliary surface */
+ assert(info->aux_surf);
+ }
+
/* The docs don't appear to say anything whatsoever about compression
* and the data port. Testing seems to indicate that the data port
* completely ignores the AuxiliarySurfaceMode field.
*/
assert(!(info->view->usage & ISL_SURF_USAGE_STORAGE_BIT));
- struct isl_tile_info tile_info;
- isl_surf_get_tile_info(info->aux_surf, &tile_info);
- uint32_t pitch_in_tiles =
- info->aux_surf->row_pitch / tile_info.phys_extent_B.width;
-
- s.AuxiliarySurfaceBaseAddress = info->aux_address;
- s.AuxiliarySurfacePitch = pitch_in_tiles - 1;
-
-#if GEN_GEN >= 8
- assert(GEN_GEN >= 9 || info->aux_usage != ISL_AUX_USAGE_CCS_E);
- /* Auxiliary surfaces in ISL have compressed formats but the hardware
- * doesn't expect our definition of the compression, it expects qpitch
- * in units of samples on the main surface.
- */
- s.AuxiliarySurfaceQPitch =
- isl_surf_get_array_pitch_sa_rows(info->aux_surf) >> 2;
-
if (info->aux_usage == ISL_AUX_USAGE_HIZ) {
/* The number of samples must be 1 */
assert(info->surf->samples == 1);
}
}
+#if GEN_GEN >= 8
s.AuxiliarySurfaceMode = isl_to_gen_aux_mode[info->aux_usage];
#else
- assert(info->aux_usage == ISL_AUX_USAGE_MCS ||
- info->aux_usage == ISL_AUX_USAGE_CCS_D);
s.MCSEnable = true;
#endif
}
-#endif
+
+ /* The auxiliary buffer info is filled when it's useable by the HW. On
+ * gen12 and above, CCS is controlled by the aux table and not the
+ * auxiliary surface information in SURFACE_STATE.
+ */
+ if (info->aux_usage != ISL_AUX_USAGE_NONE &&
+ ((info->aux_usage != ISL_AUX_USAGE_MC &&
+ info->aux_usage != ISL_AUX_USAGE_CCS_E) || GEN_GEN <= 11)) {
+
+ assert(info->aux_surf != NULL);
+
+ struct isl_tile_info tile_info;
+ isl_surf_get_tile_info(info->aux_surf, &tile_info);
+ uint32_t pitch_in_tiles =
+ info->aux_surf->row_pitch_B / tile_info.phys_extent_B.width;
+
+ s.AuxiliarySurfaceBaseAddress = info->aux_address;
+ s.AuxiliarySurfacePitch = pitch_in_tiles - 1;
#if GEN_GEN >= 8
+ /* Auxiliary surfaces in ISL have compressed formats but the hardware
+ * doesn't expect our definition of the compression, it expects qpitch
+ * in units of samples on the main surface.
+ */
+ s.AuxiliarySurfaceQPitch =
+ isl_surf_get_array_pitch_sa_rows(info->aux_surf) >> 2;
+#endif
+ }
+#endif
+
+#if GEN_GEN >= 8 && GEN_GEN < 11
/* From the CHV PRM, Volume 2d, page 321 (RENDER_SURFACE_STATE dword 0
* bit 9 "Sampler L2 Bypass Mode Disable" Programming Notes):
*
#endif
if (info->aux_usage != ISL_AUX_USAGE_NONE) {
-#if GEN_GEN >= 9
- s.RedClearColor = info->clear_color.u32[0];
- s.GreenClearColor = info->clear_color.u32[1];
- s.BlueClearColor = info->clear_color.u32[2];
- s.AlphaClearColor = info->clear_color.u32[3];
+ if (info->use_clear_address) {
+#if GEN_GEN >= 10
+ s.ClearValueAddressEnable = true;
+ s.ClearValueAddress = info->clear_address;
+#else
+ unreachable("Gen9 and earlier do not support indirect clear colors");
+#endif
+ }
+
+#if GEN_GEN == 11
+ /*
+ * From BXML > GT > Shared Functions > vol5c Shared Functions >
+ * [Structure] RENDER_SURFACE_STATE [BDW+] > ClearColorConversionEnable:
+ *
+ * Project: Gen11
+ *
+ * "Enables Pixel backend hw to convert clear values into native format
+ * and write back to clear address, so that display and sampler can use
+ * the converted value for resolving fast cleared RTs."
+ *
+ * Summary:
+ * Clear color conversion must be enabled if the clear color is stored
+ * indirectly and fast color clears are enabled.
+ */
+ if (info->use_clear_address) {
+ s.ClearColorConversionEnable = true;
+ }
+#endif
+
+#if GEN_GEN >= 12
+ assert(info->use_clear_address);
+#elif GEN_GEN >= 9
+ if (!info->use_clear_address) {
+ s.RedClearColor = info->clear_color.u32[0];
+ s.GreenClearColor = info->clear_color.u32[1];
+ s.BlueClearColor = info->clear_color.u32[2];
+ s.AlphaClearColor = info->clear_color.u32[3];
+ }
#elif GEN_GEN >= 7
/* Prior to Sky Lake, we only have one bit for the clear color which
* gives us 0 or 1 in whatever the surface's format happens to be.
}
void
-isl_genX(buffer_fill_state_s)(void *state,
+isl_genX(buffer_fill_state_s)(const struct isl_device *dev, void *state,
const struct isl_buffer_fill_state_info *restrict info)
{
- uint32_t num_elements = info->size / info->stride;
+ uint64_t buffer_size = info->size_B;
+
+ /* Uniform and Storage buffers need to have surface size not less that the
+ * aligned 32-bit size of the buffer. To calculate the array lenght on
+ * unsized arrays in StorageBuffer the last 2 bits store the padding size
+ * added to the surface, so we can calculate latter the original buffer
+ * size to know the number of elements.
+ *
+ * surface_size = isl_align(buffer_size, 4) +
+ * (isl_align(buffer_size) - buffer_size)
+ *
+ * buffer_size = (surface_size & ~3) - (surface_size & 3)
+ */
+ if (info->format == ISL_FORMAT_RAW ||
+ info->stride_B < isl_format_get_layout(info->format)->bpb / 8) {
+ assert(info->stride_B == 1);
+ uint64_t aligned_size = isl_align(buffer_size, 4);
+ buffer_size = aligned_size + (aligned_size - buffer_size);
+ }
+
+ uint32_t num_elements = buffer_size / info->stride_B;
if (GEN_GEN >= 7) {
/* From the IVB PRM, SURFACE_STATE::Height,
struct GENX(RENDER_SURFACE_STATE) s = { 0, };
s.SurfaceType = SURFTYPE_BUFFER;
- s.SurfaceFormat = (enum GENX(SURFACE_FORMAT)) info->format;
+ s.SurfaceFormat = info->format;
#if GEN_GEN >= 6
s.SurfaceVerticalAlignment = isl_to_gen_valign[4];
s.Depth = ((num_elements - 1) >> 20) & 0x7f;
#endif
- s.SurfacePitch = info->stride - 1;
+ if (GEN_GEN == 12 && dev->info->revision == 0) {
+ /* TGL-LP A0 has a HW bug (fixed in later HW) which causes buffer
+ * textures with very close base addresses (delta < 64B) to corrupt each
+ * other. We can sort-of work around this by making small buffer
+ * textures 1D textures instead. This doesn't fix the problem for large
+ * buffer textures but the liklihood of large, overlapping, and very
+ * close buffer textures is fairly low and the point is to hack around
+ * the bug so we can run apps and tests.
+ */
+ if (info->format != ISL_FORMAT_RAW &&
+ info->stride_B == isl_format_get_layout(info->format)->bpb / 8 &&
+ num_elements <= (1 << 14)) {
+ s.SurfaceType = SURFTYPE_1D;
+ s.Width = num_elements - 1;
+ s.Height = 0;
+ s.Depth = 0;
+ }
+ }
+
+ s.SurfacePitch = info->stride_B - 1;
#if GEN_GEN >= 6
s.NumberofMultisamples = MULTISAMPLECOUNT_1;
#endif
#if (GEN_GEN >= 8 || GEN_IS_HASWELL)
- s.ShaderChannelSelectRed = SCS_RED;
- s.ShaderChannelSelectGreen = SCS_GREEN;
- s.ShaderChannelSelectBlue = SCS_BLUE;
- s.ShaderChannelSelectAlpha = SCS_ALPHA;
+ s.ShaderChannelSelectRed = (enum GENX(ShaderChannelSelect)) info->swizzle.r;
+ s.ShaderChannelSelectGreen = (enum GENX(ShaderChannelSelect)) info->swizzle.g;
+ s.ShaderChannelSelectBlue = (enum GENX(ShaderChannelSelect)) info->swizzle.b;
+ s.ShaderChannelSelectAlpha = (enum GENX(ShaderChannelSelect)) info->swizzle.a;
#endif
GENX(RENDER_SURFACE_STATE_pack)(NULL, state, &s);
{
struct GENX(RENDER_SURFACE_STATE) s = {
.SurfaceType = SURFTYPE_NULL,
- .SurfaceFormat = (enum GENX(SURFACE_FORMAT)) ISL_FORMAT_B8G8R8A8_UNORM,
+ /* We previously had this format set to B8G8R8A8_UNORM but ran into
+ * hangs on IVB. R32_UINT seems to work for everybody.
+ *
+ * https://gitlab.freedesktop.org/mesa/mesa/issues/1872
+ */
+ .SurfaceFormat = ISL_FORMAT_R32_UINT,
#if GEN_GEN >= 7
- .SurfaceArray = size.depth > 0,
+ .SurfaceArray = size.depth > 1,
#endif
#if GEN_GEN >= 8
.TileMode = YMAJOR,
#else
.TiledSurface = true,
.TileWalk = TILEWALK_YMAJOR,
+#endif
+#if GEN_GEN == 7
+ /* According to PRMs: "Volume 4 Part 1: Subsystem and Cores – Shared
+ * Functions"
+ *
+ * RENDER_SURFACE_STATE::Surface Vertical Alignment
+ *
+ * "This field must be set to VALIGN_4 for all tiled Y Render Target
+ * surfaces."
+ *
+ * Affect IVB, HSW.
+ */
+ .SurfaceVerticalAlignment = VALIGN_4,
#endif
.Width = size.width - 1,
.Height = size.height - 1,
projects / mesa.git / blobdiff