intel/dump_gpu: further track mapping of BOs

[mesa.git] / src / intel / isl / isl_surface_state.c

diff --git a/src/intel/isl/isl_surface_state.c b/src/intel/isl/isl_surface_state.c
index 0145be160c7ba73ed8f3c8255b4461bf268c9a6c..e44d5f74137c0a00c173bcefab93bedcfa0019f3 100644 (file)
--- a/src/intel/isl/isl_surface_state.c
+++ b/src/intel/isl/isl_surface_state.c
@@ -90,6 +90,7 @@ static const uint32_t isl_to_gen_multisample_layout[] = {
 static const uint32_t isl_to_gen_aux_mode[] = {
    [ISL_AUX_USAGE_NONE] = AUX_NONE,
    [ISL_AUX_USAGE_MCS] = AUX_CCS_E,
+   [ISL_AUX_USAGE_GEN12_CCS_E] = AUX_CCS_E,
    [ISL_AUX_USAGE_CCS_E] = AUX_CCS_E,
    [ISL_AUX_USAGE_HIZ_CCS_WT] = AUX_CCS_E,
    [ISL_AUX_USAGE_MCS_CCS] = AUX_MCS_LCE,
@@ -284,8 +285,36 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state,
    s.SurfaceFormat = info->view->format;
 
 #if GEN_GEN >= 12
-   s.DepthStencilResource =
-      isl_surf_usage_is_depth_or_stencil(info->surf->usage);
+   /* The BSpec description of this field says:
+    *
+    *    "This bit field, when set, indicates if the resource is created as
+    *    Depth/Stencil resource."
+    *
+    *    "SW must set this bit for any resource that was created with
+    *    Depth/Stencil resource flag. Setting this bit allows HW to properly
+    *    interpret the data-layout for various cases. For any resource that's
+    *    created without Depth/Stencil resource flag, it must be reset."
+    *
+    * Even though the docs for this bit seem to imply that it's required for
+    * anything which might have been used for depth/stencil, empirical
+    * evidence suggests that it only affects CCS compression usage.  There are
+    * a few things which back this up:
+    *
+    *  1. The docs are also pretty clear that this bit was added as part
+    *     of enabling Gen12 depth/stencil lossless compression.
+    *
+    *  2. The only new difference between depth/stencil and color images on
+    *     Gen12 (where the bit was added) is how they treat CCS compression.
+    *     All other differences such as alignment requirements and MSAA layout
+    *     are already covered by other bits.
+    *
+    * Under these assumptions, it makes sense for ISL to model this bit as
+    * being an extension of AuxiliarySurfaceMode where STC_CCS and HIZ_CCS_WT
+    * are indicated by AuxiliarySurfaceMode == CCS_E and DepthStencilResource
+    * == true.
+    */
+   s.DepthStencilResource = info->aux_usage == ISL_AUX_USAGE_HIZ_CCS_WT ||
+                            info->aux_usage == ISL_AUX_USAGE_STC_CCS;
 #endif
 
 #if GEN_GEN <= 5
@@ -561,6 +590,7 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state,
       if (GEN_GEN >= 12) {
          assert(info->aux_usage == ISL_AUX_USAGE_MCS ||
                 info->aux_usage == ISL_AUX_USAGE_CCS_E ||
+                info->aux_usage == ISL_AUX_USAGE_GEN12_CCS_E ||
                 info->aux_usage == ISL_AUX_USAGE_HIZ_CCS_WT ||
                 info->aux_usage == ISL_AUX_USAGE_MCS_CCS ||
                 info->aux_usage == ISL_AUX_USAGE_STC_CCS);
@@ -581,12 +611,18 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state,
       /* The docs don't appear to say anything whatsoever about compression
        * and the data port.  Testing seems to indicate that the data port
        * completely ignores the AuxiliarySurfaceMode field.
+       *
+       * On gen12 HDC supports compression.
        */
-      assert(!(info->view->usage & ISL_SURF_USAGE_STORAGE_BIT));
+      if (GEN_GEN < 12)
+         assert(!(info->view->usage & ISL_SURF_USAGE_STORAGE_BIT));
 
       if (isl_surf_usage_is_depth(info->surf->usage))
          assert(isl_aux_usage_has_hiz(info->aux_usage));
 
+      if (isl_surf_usage_is_stencil(info->surf->usage))
+         assert(info->aux_usage == ISL_AUX_USAGE_STC_CCS);
+
       if (isl_aux_usage_has_hiz(info->aux_usage)) {
          /* For Gen8-10, there are some restrictions around sampling from HiZ.
           * The Skylake PRM docs for RENDER_SURFACE_STATE::AuxiliarySurfaceMode
@@ -894,7 +930,7 @@ isl_genX(null_fill_state)(void *state, struct isl_extent3d size)
       /* We previously had this format set to B8G8R8A8_UNORM but ran into
        * hangs on IVB. R32_UINT seems to work for everybody.
        *
-       * https://gitlab.freedesktop.org/mesa/mesa/issues/1872
+       * https://gitlab.freedesktop.org/mesa/mesa/-/issues/1872
        */
       .SurfaceFormat = ISL_FORMAT_R32_UINT,
 #if GEN_GEN >= 7