[ISL_TILING_Y0] = YMAJOR,
[ISL_TILING_Yf] = YMAJOR,
[ISL_TILING_Ys] = YMAJOR,
+#if GEN_GEN <= 11
[ISL_TILING_W] = WMAJOR,
+#endif
};
#endif
};
#endif
-#if GEN_GEN >= 9
+#if GEN_GEN >= 12
+static const uint32_t isl_to_gen_aux_mode[] = {
+ [ISL_AUX_USAGE_NONE] = AUX_NONE,
+ [ISL_AUX_USAGE_MCS] = AUX_CCS_E,
+ [ISL_AUX_USAGE_CCS_E] = AUX_CCS_E,
+ [ISL_AUX_USAGE_MCS_CCS] = AUX_MCS_LCE,
+};
+#elif GEN_GEN >= 9
static const uint32_t isl_to_gen_aux_mode[] = {
[ISL_AUX_USAGE_NONE] = AUX_NONE,
[ISL_AUX_USAGE_HIZ] = AUX_HIZ,
s.SurfaceFormat = info->view->format;
+#if GEN_GEN >= 12
+ s.DepthStencilResource =
+ isl_surf_usage_is_depth_or_stencil(info->surf->usage);
+#endif
+
#if GEN_GEN <= 5
s.ColorBufferComponentWriteDisables = info->write_disables;
#else
unreachable("bad SurfaceType");
}
-#if GEN_GEN >= 7
+#if GEN_GEN >= 12
+ /* GEN:BUG:1806565034: Only set SurfaceArray if arrayed surface is > 1. */
+ s.SurfaceArray = info->surf->dim != ISL_SURF_DIM_3D &&
+ info->view->array_len > 1;
+#elif GEN_GEN >= 7
s.SurfaceArray = info->surf->dim != ISL_SURF_DIM_3D;
#endif
#endif
#if GEN_GEN >= 8
+ assert(GEN_GEN < 12 || info->surf->tiling != ISL_TILING_W);
s.TileMode = isl_to_gen_tiling[info->surf->tiling];
#else
s.TiledSurface = info->surf->tiling != ISL_TILING_LINEAR,
#endif
#if GEN_GEN >= 7
- if (info->aux_surf && info->aux_usage != ISL_AUX_USAGE_NONE) {
+ if (info->aux_usage != ISL_AUX_USAGE_NONE) {
+ /* Check valid aux usages per-gen */
+ if (GEN_GEN >= 12) {
+ assert(info->aux_usage == ISL_AUX_USAGE_MCS ||
+ info->aux_usage == ISL_AUX_USAGE_CCS_E ||
+ info->aux_usage == ISL_AUX_USAGE_MCS_CCS);
+ } else if (GEN_GEN >= 9) {
+ assert(info->aux_usage == ISL_AUX_USAGE_HIZ ||
+ info->aux_usage == ISL_AUX_USAGE_MCS ||
+ info->aux_usage == ISL_AUX_USAGE_CCS_D ||
+ info->aux_usage == ISL_AUX_USAGE_CCS_E);
+ } else if (GEN_GEN >= 8) {
+ assert(info->aux_usage == ISL_AUX_USAGE_HIZ ||
+ info->aux_usage == ISL_AUX_USAGE_MCS ||
+ info->aux_usage == ISL_AUX_USAGE_CCS_D);
+ } else if (GEN_GEN >= 7) {
+ assert(info->aux_usage == ISL_AUX_USAGE_MCS ||
+ info->aux_usage == ISL_AUX_USAGE_CCS_D);
+ }
+
/* The docs don't appear to say anything whatsoever about compression
* and the data port. Testing seems to indicate that the data port
* completely ignores the AuxiliarySurfaceMode field.
*/
assert(!(info->view->usage & ISL_SURF_USAGE_STORAGE_BIT));
- struct isl_tile_info tile_info;
- isl_surf_get_tile_info(info->aux_surf, &tile_info);
- uint32_t pitch_in_tiles =
- info->aux_surf->row_pitch_B / tile_info.phys_extent_B.width;
-
- s.AuxiliarySurfaceBaseAddress = info->aux_address;
- s.AuxiliarySurfacePitch = pitch_in_tiles - 1;
-
-#if GEN_GEN >= 8
- assert(GEN_GEN >= 9 || info->aux_usage != ISL_AUX_USAGE_CCS_E);
- /* Auxiliary surfaces in ISL have compressed formats but the hardware
- * doesn't expect our definition of the compression, it expects qpitch
- * in units of samples on the main surface.
- */
- s.AuxiliarySurfaceQPitch =
- isl_surf_get_array_pitch_sa_rows(info->aux_surf) >> 2;
-
if (info->aux_usage == ISL_AUX_USAGE_HIZ) {
/* The number of samples must be 1 */
assert(info->surf->samples == 1);
}
}
+#if GEN_GEN >= 8
s.AuxiliarySurfaceMode = isl_to_gen_aux_mode[info->aux_usage];
#else
- assert(info->aux_usage == ISL_AUX_USAGE_MCS ||
- info->aux_usage == ISL_AUX_USAGE_CCS_D);
s.MCSEnable = true;
+#endif
+ }
+
+ /* The auxiliary buffer info is filled when it's useable by the HW.
+ *
+ * Starting with Gen12, the only form of compression that can be used
+ * with RENDER_SURFACE_STATE which requires an aux surface is MCS.
+ * HiZ still requires a surface but the HiZ surface can only be
+ * accessed through 3DSTATE_HIER_DEPTH_BUFFER.
+ *
+ * On all earlier hardware, an aux surface is required for all forms
+ * of compression.
+ */
+ if ((GEN_GEN < 12 && info->aux_usage != ISL_AUX_USAGE_NONE) ||
+ (GEN_GEN >= 12 && isl_aux_usage_has_mcs(info->aux_usage))) {
+
+ assert(info->aux_surf != NULL);
+
+ struct isl_tile_info tile_info;
+ isl_surf_get_tile_info(info->aux_surf, &tile_info);
+ uint32_t pitch_in_tiles =
+ info->aux_surf->row_pitch_B / tile_info.phys_extent_B.width;
+
+ s.AuxiliarySurfaceBaseAddress = info->aux_address;
+ s.AuxiliarySurfacePitch = pitch_in_tiles - 1;
+
+#if GEN_GEN >= 8
+ /* Auxiliary surfaces in ISL have compressed formats but the hardware
+ * doesn't expect our definition of the compression, it expects qpitch
+ * in units of samples on the main surface.
+ */
+ s.AuxiliarySurfaceQPitch =
+ isl_surf_get_array_pitch_sa_rows(info->aux_surf) >> 2;
#endif
}
#endif
}
#endif
-#if GEN_GEN >= 9
+#if GEN_GEN >= 12
+ assert(info->use_clear_address);
+#elif GEN_GEN >= 9
if (!info->use_clear_address) {
s.RedClearColor = info->clear_color.u32[0];
s.GreenClearColor = info->clear_color.u32[1];
}
void
-isl_genX(buffer_fill_state_s)(void *state,
+isl_genX(buffer_fill_state_s)(const struct isl_device *dev, void *state,
const struct isl_buffer_fill_state_info *restrict info)
{
uint64_t buffer_size = info->size_B;
s.Depth = ((num_elements - 1) >> 20) & 0x7f;
#endif
+ if (GEN_GEN == 12 && dev->info->revision == 0) {
+ /* TGL-LP A0 has a HW bug (fixed in later HW) which causes buffer
+ * textures with very close base addresses (delta < 64B) to corrupt each
+ * other. We can sort-of work around this by making small buffer
+ * textures 1D textures instead. This doesn't fix the problem for large
+ * buffer textures but the liklihood of large, overlapping, and very
+ * close buffer textures is fairly low and the point is to hack around
+ * the bug so we can run apps and tests.
+ */
+ if (info->format != ISL_FORMAT_RAW &&
+ info->stride_B == isl_format_get_layout(info->format)->bpb / 8 &&
+ num_elements <= (1 << 14)) {
+ s.SurfaceType = SURFTYPE_1D;
+ s.Width = num_elements - 1;
+ s.Height = 0;
+ s.Depth = 0;
+ }
+ }
+
s.SurfacePitch = info->stride_B - 1;
#if GEN_GEN >= 6