#define __gen_address_type uint64_t
#define __gen_user_data void
-static inline uint64_t
-__gen_combine_address(void *data, void *loc, uint64_t addr, uint32_t delta)
+static uint64_t
+__gen_combine_address(__attribute__((unused)) void *data,
+ __attribute__((unused)) void *loc, uint64_t addr,
+ uint32_t delta)
{
return addr + delta;
}
#include "isl_priv.h"
-#define __PASTE2(x, y) x ## y
-#define __PASTE(x, y) __PASTE2(x, y)
-#define isl_genX(x) __PASTE(isl_, genX(x))
-
#if GEN_GEN >= 8
static const uint8_t isl_to_gen_halign[] = {
[4] = HALIGN4,
assert(!(usage & ISL_SURF_USAGE_CUBE_BIT));
return SURFTYPE_1D;
case ISL_SURF_DIM_2D:
- if (usage & ISL_SURF_USAGE_STORAGE_BIT) {
- /* Storage images are always plain 2-D, not cube */
- return SURFTYPE_2D;
- } else if (usage & ISL_SURF_USAGE_CUBE_BIT) {
+ if ((usage & ISL_SURF_USAGE_CUBE_BIT) &&
+ (usage & ISL_SURF_USAGE_TEXTURE_BIT)) {
+ /* We need SURFTYPE_CUBE to make cube sampling work */
return SURFTYPE_CUBE;
} else {
+ /* Everything else (render and storage) treat cubes as plain
+ * 2D array textures
+ */
return SURFTYPE_2D;
}
case ISL_SURF_DIM_3D:
* hardware. Note that this does NOT give you the actual hardware enum values
* but an index into the isl_to_gen_[hv]align arrays above.
*/
-static inline struct isl_extent3d
+UNUSED static struct isl_extent3d
get_image_alignment(const struct isl_surf *surf)
{
if (GEN_GEN >= 9) {
default:
unreachable("Bad isl_surf_dim");
case ISL_DIM_LAYOUT_GEN4_2D:
- case ISL_DIM_LAYOUT_GEN4_3D:
if (GEN_GEN >= 9) {
- return isl_surf_get_array_pitch_el_rows(surf);
+ if (surf->dim == ISL_SURF_DIM_3D && surf->tiling == ISL_TILING_W) {
+ /* This is rather annoying and completely undocumented. It
+ * appears that the hardware has a bug (or undocumented feature)
+ * regarding stencil buffers most likely related to the way
+ * W-tiling is handled as modified Y-tiling. If you bind a 3-D
+ * stencil buffer normally, and use texelFetch on it, the z or
+ * array index will get implicitly multiplied by 2 for no obvious
+ * reason. The fix appears to be to divide qpitch by 2 for
+ * W-tiled surfaces.
+ */
+ return isl_surf_get_array_pitch_el_rows(surf) / 2;
+ } else {
+ return isl_surf_get_array_pitch_el_rows(surf);
+ }
} else {
/* From the Broadwell PRM for RENDER_SURFACE_STATE.QPitch
*
* slices.
*/
return isl_surf_get_array_pitch_el(surf);
+ case ISL_DIM_LAYOUT_GEN4_3D:
+ /* QPitch doesn't make sense for ISL_DIM_LAYOUT_GEN4_3D since it uses a
+ * different pitch at each LOD. Also, the QPitch field is ignored for
+ * these surfaces. From the Broadwell PRM documentation for QPitch:
+ *
+ * This field specifies the distance in rows between array slices. It
+ * is used only in the following cases:
+ * - Surface Array is enabled OR
+ * - Number of Mulitsamples is not NUMSAMPLES_1 and Multisampled
+ * Surface Storage Format set to MSFMT_MSS OR
+ * - Surface Type is SURFTYPE_CUBE
+ *
+ * None of the three conditions above can possibly apply to a 3D surface
+ * so it is safe to just set QPitch to 0.
+ */
+ return 0;
}
}
#endif /* GEN_GEN >= 8 */
struct GENX(RENDER_SURFACE_STATE) s = { 0 };
s.SurfaceType = get_surftype(info->surf->dim, info->view->usage);
+
+ if (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT)
+ assert(isl_format_supports_rendering(dev->info, info->view->format));
+ else if (info->view->usage & ISL_SURF_USAGE_TEXTURE_BIT)
+ assert(isl_format_supports_sampling(dev->info, info->view->format));
+
+ /* From the Sky Lake PRM Vol. 2d, RENDER_SURFACE_STATE::SurfaceFormat
+ *
+ * This field cannot be a compressed (BC*, DXT*, FXT*, ETC*, EAC*)
+ * format if the Surface Type is SURFTYPE_1D
+ */
+ if (info->surf->dim == ISL_SURF_DIM_1D)
+ assert(!isl_format_is_compressed(info->view->format));
+
+ if (isl_format_is_compressed(info->surf->format)) {
+ /* You're not allowed to make a view of a compressed format with any
+ * format other than the surface format. None of the userspace APIs
+ * allow for this directly and doing so would mess up a number of
+ * surface parameters such as Width, Height, and alignments. Ideally,
+ * we'd like to assert that the two formats match. However, we have an
+ * S3TC workaround that requires us to do reinterpretation. So assert
+ * that they're at least the same bpb and block size.
+ */
+ MAYBE_UNUSED const struct isl_format_layout *surf_fmtl =
+ isl_format_get_layout(info->surf->format);
+ MAYBE_UNUSED const struct isl_format_layout *view_fmtl =
+ isl_format_get_layout(info->surf->format);
+ assert(surf_fmtl->bpb == view_fmtl->bpb);
+ assert(surf_fmtl->bw == view_fmtl->bw);
+ assert(surf_fmtl->bh == view_fmtl->bh);
+ }
+
s.SurfaceFormat = info->view->format;
+#if GEN_GEN <= 5
+ s.ColorBufferComponentWriteDisables = info->write_disables;
+#else
+ assert(info->write_disables == 0);
+#endif
+
#if GEN_IS_HASWELL
- s.IntegerSurfaceFormat = isl_format_has_int_channel(s.SurfaceFormat);
+ s.IntegerSurfaceFormat =
+ isl_format_has_int_channel((enum isl_format) s.SurfaceFormat);
#endif
+ assert(info->surf->logical_level0_px.width > 0 &&
+ info->surf->logical_level0_px.height > 0);
+
s.Width = info->surf->logical_level0_px.width - 1;
s.Height = info->surf->logical_level0_px.height - 1;
switch (s.SurfaceType) {
case SURFTYPE_1D:
case SURFTYPE_2D:
+ /* From the Ivy Bridge PRM >> RENDER_SURFACE_STATE::MinimumArrayElement:
+ *
+ * "If Number of Multisamples is not MULTISAMPLECOUNT_1, this field
+ * must be set to zero if this surface is used with sampling engine
+ * messages."
+ *
+ * This restriction appears to exist only on Ivy Bridge.
+ */
+ if (GEN_GEN == 7 && !GEN_IS_HASWELL && !ISL_DEV_IS_BAYTRAIL(dev) &&
+ (info->view->usage & ISL_SURF_USAGE_TEXTURE_BIT) &&
+ info->surf->samples > 1)
+ assert(info->view->base_array_layer == 0);
+
s.MinimumArrayElement = info->view->base_array_layer;
/* From the Broadwell PRM >> RENDER_SURFACE_STATE::Depth:
s.RenderTargetViewExtent = s.Depth;
break;
case SURFTYPE_3D:
- s.MinimumArrayElement = info->view->base_array_layer;
-
/* From the Broadwell PRM >> RENDER_SURFACE_STATE::Depth:
*
* If the volume texture is MIP-mapped, this field specifies the
* textures with more levels than we can render to. In order to prevent
* assert-failures in the packing function below, we only set the field
* when it's actually going to be used by the hardware.
+ *
+ * Similaraly, the MinimumArrayElement field is ignored by all hardware
+ * prior to Sky Lake when texturing and we want it set to 0 anyway.
+ * Since it's already initialized to 0, we can just leave it alone for
+ * texture surfaces.
*/
if (info->view->usage & (ISL_SURF_USAGE_RENDER_TARGET_BIT |
ISL_SURF_USAGE_STORAGE_BIT)) {
- s.RenderTargetViewExtent = isl_minify(info->surf->logical_level0_px.depth,
- info->view->base_level) - 1;
+ s.MinimumArrayElement = info->view->base_array_layer;
+ s.RenderTargetViewExtent = info->view->array_len - 1;
}
break;
default:
s.RenderCacheReadWriteMode = 0;
#endif
- if (info->view->usage & ISL_SURF_USAGE_CUBE_BIT) {
-#if GEN_GEN >= 8
- s.CubeFaceEnablePositiveZ = 1;
- s.CubeFaceEnableNegativeZ = 1;
- s.CubeFaceEnablePositiveY = 1;
- s.CubeFaceEnableNegativeY = 1;
- s.CubeFaceEnablePositiveX = 1;
- s.CubeFaceEnableNegativeX = 1;
-#else
- s.CubeFaceEnables = 0x3f;
-#endif
- }
+ s.CubeFaceEnablePositiveZ = 1;
+ s.CubeFaceEnableNegativeZ = 1;
+ s.CubeFaceEnablePositiveY = 1;
+ s.CubeFaceEnableNegativeY = 1;
+ s.CubeFaceEnablePositiveX = 1;
+ s.CubeFaceEnableNegativeX = 1;
#if GEN_GEN >= 6
s.NumberofMultisamples = ffs(info->surf->samples) - 1;
#endif
#if (GEN_GEN >= 8 || GEN_IS_HASWELL)
- s.ShaderChannelSelectRed = info->view->channel_select[0];
- s.ShaderChannelSelectGreen = info->view->channel_select[1];
- s.ShaderChannelSelectBlue = info->view->channel_select[2];
- s.ShaderChannelSelectAlpha = info->view->channel_select[3];
+ if (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT)
+ assert(isl_swizzle_supports_rendering(dev->info, info->view->swizzle));
+
+ s.ShaderChannelSelectRed = (enum GENX(ShaderChannelSelect)) info->view->swizzle.r;
+ s.ShaderChannelSelectGreen = (enum GENX(ShaderChannelSelect)) info->view->swizzle.g;
+ s.ShaderChannelSelectBlue = (enum GENX(ShaderChannelSelect)) info->view->swizzle.b;
+ s.ShaderChannelSelectAlpha = (enum GENX(ShaderChannelSelect)) info->view->swizzle.a;
+#else
+ assert(isl_swizzle_is_identity(info->view->swizzle));
#endif
s.SurfaceBaseAddress = info->address;
assert(info->surf->levels == 1);
assert(info->surf->logical_level0_px.array_len == 1);
assert(info->aux_usage == ISL_AUX_USAGE_NONE);
+
+ if (GEN_GEN >= 8) {
+ /* Broadwell added more rules. */
+ assert(info->surf->samples == 1);
+ if (isl_format_get_layout(info->view->format)->bpb == 8)
+ assert(info->x_offset_sa % 16 == 0);
+ if (isl_format_get_layout(info->view->format)->bpb == 16)
+ assert(info->x_offset_sa % 8 == 0);
+ }
+
#if GEN_GEN >= 7
s.SurfaceArray = false;
#endif
#if GEN_GEN >= 7
if (info->aux_surf && info->aux_usage != ISL_AUX_USAGE_NONE) {
+ /* The docs don't appear to say anything whatsoever about compression
+ * and the data port. Testing seems to indicate that the data port
+ * completely ignores the AuxiliarySurfaceMode field.
+ */
+ assert(!(info->view->usage & ISL_SURF_USAGE_STORAGE_BIT));
+
struct isl_tile_info tile_info;
- isl_surf_get_tile_info(dev, info->aux_surf, &tile_info);
+ isl_surf_get_tile_info(info->aux_surf, &tile_info);
uint32_t pitch_in_tiles =
info->aux_surf->row_pitch / tile_info.phys_extent_B.width;
+ s.AuxiliarySurfaceBaseAddress = info->aux_address;
+ s.AuxiliarySurfacePitch = pitch_in_tiles - 1;
+
#if GEN_GEN >= 8
assert(GEN_GEN >= 9 || info->aux_usage != ISL_AUX_USAGE_CCS_E);
- s.AuxiliarySurfacePitch = pitch_in_tiles - 1;
/* Auxiliary surfaces in ISL have compressed formats but the hardware
* doesn't expect our definition of the compression, it expects qpitch
* in units of samples on the main surface.
*/
s.AuxiliarySurfaceQPitch =
isl_surf_get_array_pitch_sa_rows(info->aux_surf) >> 2;
- s.AuxiliarySurfaceBaseAddress = info->aux_address;
+
+ if (info->aux_usage == ISL_AUX_USAGE_HIZ) {
+ /* The number of samples must be 1 */
+ assert(info->surf->samples == 1);
+
+ /* The dimension must not be 3D */
+ assert(info->surf->dim != ISL_SURF_DIM_3D);
+
+ /* The format must be one of the following: */
+ switch (info->view->format) {
+ case ISL_FORMAT_R32_FLOAT:
+ case ISL_FORMAT_R24_UNORM_X8_TYPELESS:
+ case ISL_FORMAT_R16_UNORM:
+ break;
+ default:
+ assert(!"Incompatible HiZ Sampling format");
+ break;
+ }
+ }
+
s.AuxiliarySurfaceMode = isl_to_gen_aux_mode[info->aux_usage];
#else
assert(info->aux_usage == ISL_AUX_USAGE_MCS ||
info->aux_usage == ISL_AUX_USAGE_CCS_D);
- s.MCSBaseAddress = info->aux_address,
- s.MCSSurfacePitch = pitch_in_tiles - 1;
s.MCSEnable = true;
#endif
}
s.SamplerL2BypassModeDisable = true;
break;
default:
+ /* From the SKL PRM, Programming Note under Sampler Output Channel
+ * Mapping:
+ *
+ * If a surface has an associated HiZ Auxilliary surface, the
+ * Sampler L2 Bypass Mode Disable field in the RENDER_SURFACE_STATE
+ * must be set.
+ */
+ if (GEN_GEN >= 9 && info->aux_usage == ISL_AUX_USAGE_HIZ)
+ s.SamplerL2BypassModeDisable = true;
break;
}
}
#endif
+ if (info->aux_usage != ISL_AUX_USAGE_NONE) {
+ if (info->use_clear_address) {
+#if GEN_GEN >= 10
+ s.ClearValueAddressEnable = true;
+ s.ClearValueAddress = info->clear_address;
+#else
+ unreachable("Gen9 and earlier do not support indirect clear colors");
+#endif
+ }
#if GEN_GEN >= 9
- s.RedClearColor = info->clear_color.u32[0];
- s.GreenClearColor = info->clear_color.u32[1];
- s.BlueClearColor = info->clear_color.u32[2];
- s.AlphaClearColor = info->clear_color.u32[3];
-#elif GEN_GEN >= 7
- /* Prior to Sky Lake, we only have one bit for the clear color which
- * gives us 0 or 1 in whatever the surface's format happens to be.
- */
- if (isl_format_has_int_channel(info->view->format)) {
- for (unsigned i = 0; i < 4; i++) {
- assert(info->clear_color.u32[i] == 0 ||
- info->clear_color.u32[i] == 1);
+ if (!info->use_clear_address) {
+ s.RedClearColor = info->clear_color.u32[0];
+ s.GreenClearColor = info->clear_color.u32[1];
+ s.BlueClearColor = info->clear_color.u32[2];
+ s.AlphaClearColor = info->clear_color.u32[3];
}
- s.RedClearColor = info->clear_color.u32[0] != 0;
- s.GreenClearColor = info->clear_color.u32[1] != 0;
- s.BlueClearColor = info->clear_color.u32[2] != 0;
- s.AlphaClearColor = info->clear_color.u32[3] != 0;
- } else {
- for (unsigned i = 0; i < 4; i++) {
- assert(info->clear_color.f32[i] == 0.0f ||
- info->clear_color.f32[i] == 1.0f);
+#elif GEN_GEN >= 7
+ /* Prior to Sky Lake, we only have one bit for the clear color which
+ * gives us 0 or 1 in whatever the surface's format happens to be.
+ */
+ if (isl_format_has_int_channel(info->view->format)) {
+ for (unsigned i = 0; i < 4; i++) {
+ assert(info->clear_color.u32[i] == 0 ||
+ info->clear_color.u32[i] == 1);
+ }
+ s.RedClearColor = info->clear_color.u32[0] != 0;
+ s.GreenClearColor = info->clear_color.u32[1] != 0;
+ s.BlueClearColor = info->clear_color.u32[2] != 0;
+ s.AlphaClearColor = info->clear_color.u32[3] != 0;
+ } else {
+ for (unsigned i = 0; i < 4; i++) {
+ assert(info->clear_color.f32[i] == 0.0f ||
+ info->clear_color.f32[i] == 1.0f);
+ }
+ s.RedClearColor = info->clear_color.f32[0] != 0.0f;
+ s.GreenClearColor = info->clear_color.f32[1] != 0.0f;
+ s.BlueClearColor = info->clear_color.f32[2] != 0.0f;
+ s.AlphaClearColor = info->clear_color.f32[3] != 0.0f;
}
- s.RedClearColor = info->clear_color.f32[0] != 0.0f;
- s.GreenClearColor = info->clear_color.f32[1] != 0.0f;
- s.BlueClearColor = info->clear_color.f32[2] != 0.0f;
- s.AlphaClearColor = info->clear_color.f32[3] != 0.0f;
- }
#endif
+ }
GENX(RENDER_SURFACE_STATE_pack)(NULL, state, &s);
}
isl_genX(buffer_fill_state_s)(void *state,
const struct isl_buffer_fill_state_info *restrict info)
{
- uint32_t num_elements = info->size / info->stride;
+ uint64_t buffer_size = info->size;
+
+ /* Uniform and Storage buffers need to have surface size not less that the
+ * aligned 32-bit size of the buffer. To calculate the array lenght on
+ * unsized arrays in StorageBuffer the last 2 bits store the padding size
+ * added to the surface, so we can calculate latter the original buffer
+ * size to know the number of elements.
+ *
+ * surface_size = isl_align(buffer_size, 4) +
+ * (isl_align(buffer_size) - buffer_size)
+ *
+ * buffer_size = (surface_size & ~3) - (surface_size & 3)
+ */
+ if (info->format == ISL_FORMAT_RAW ||
+ info->stride < isl_format_get_layout(info->format)->bpb / 8) {
+ assert(info->stride == 1);
+ uint64_t aligned_size = isl_align(buffer_size, 4);
+ buffer_size = aligned_size + (aligned_size - buffer_size);
+ }
+
+ uint32_t num_elements = buffer_size / info->stride;
if (GEN_GEN >= 7) {
/* From the IVB PRM, SURFACE_STATE::Height,
*/
if (info->format == ISL_FORMAT_RAW) {
assert(num_elements <= (1ull << 30));
- assert((num_elements & 3) == 0);
+ assert(num_elements > 0);
} else {
assert(num_elements <= (1ull << 27));
}
GENX(RENDER_SURFACE_STATE_pack)(NULL, state, &s);
}
+
+void
+isl_genX(null_fill_state)(void *state, struct isl_extent3d size)
+{
+ struct GENX(RENDER_SURFACE_STATE) s = {
+ .SurfaceType = SURFTYPE_NULL,
+ .SurfaceFormat = ISL_FORMAT_B8G8R8A8_UNORM,
+#if GEN_GEN >= 7
+ .SurfaceArray = size.depth > 0,
+#endif
+#if GEN_GEN >= 8
+ .TileMode = YMAJOR,
+#else
+ .TiledSurface = true,
+ .TileWalk = TILEWALK_YMAJOR,
+#endif
+ .Width = size.width - 1,
+ .Height = size.height - 1,
+ .Depth = size.depth - 1,
+ .RenderTargetViewExtent = size.depth - 1,
+#if GEN_GEN <= 5
+ .ColorBufferComponentWriteDisables = 0xf,
+#endif
+ };
+ GENX(RENDER_SURFACE_STATE_pack)(NULL, state, &s);
+}
projects / mesa.git / blobdiff