intel/isl: Add some helpers for working with RGBX formats
[mesa.git] / src / intel / isl / isl_surface_state.c
index cd8bef257fed0207e3fa5b250971f6bf624c2d7f..f181c3dfb2f2a94b96f55c37988e7f148217a4e4 100644 (file)
 #define __gen_address_type uint64_t
 #define __gen_user_data void
 
-static inline uint64_t
-__gen_combine_address(void *data, void *loc, uint64_t addr, uint32_t delta)
+static uint64_t
+__gen_combine_address(__attribute__((unused)) void *data,
+                      __attribute__((unused)) void *loc, uint64_t addr,
+                      uint32_t delta)
 {
    return addr + delta;
 }
@@ -130,7 +132,7 @@ get_surftype(enum isl_surf_dim dim, isl_surf_usage_flags_t usage)
  * hardware.  Note that this does NOT give you the actual hardware enum values
  * but an index into the isl_to_gen_[hv]align arrays above.
  */
-static inline struct isl_extent3d
+UNUSED static struct isl_extent3d
 get_image_alignment(const struct isl_surf *surf)
 {
    if (GEN_GEN >= 9) {
@@ -277,7 +279,8 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state,
 #endif
 
 #if GEN_IS_HASWELL
-   s.IntegerSurfaceFormat = isl_format_has_int_channel(s.SurfaceFormat);
+   s.IntegerSurfaceFormat =
+      isl_format_has_int_channel((enum isl_format) s.SurfaceFormat);
 #endif
 
    assert(info->surf->logical_level0_px.width > 0 &&
@@ -451,18 +454,12 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state,
    s.RenderCacheReadWriteMode = 0;
 #endif
 
-   if (info->view->usage & ISL_SURF_USAGE_CUBE_BIT) {
-#if GEN_GEN >= 8
-      s.CubeFaceEnablePositiveZ = 1;
-      s.CubeFaceEnableNegativeZ = 1;
-      s.CubeFaceEnablePositiveY = 1;
-      s.CubeFaceEnableNegativeY = 1;
-      s.CubeFaceEnablePositiveX = 1;
-      s.CubeFaceEnableNegativeX = 1;
-#else
-      s.CubeFaceEnables = 0x3f;
-#endif
-   }
+   s.CubeFaceEnablePositiveZ = 1;
+   s.CubeFaceEnableNegativeZ = 1;
+   s.CubeFaceEnablePositiveY = 1;
+   s.CubeFaceEnableNegativeY = 1;
+   s.CubeFaceEnablePositiveX = 1;
+   s.CubeFaceEnableNegativeX = 1;
 
 #if GEN_GEN >= 6
    s.NumberofMultisamples = ffs(info->surf->samples) - 1;
@@ -473,42 +470,15 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state,
 #endif
 
 #if (GEN_GEN >= 8 || GEN_IS_HASWELL)
-   if (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) {
-      /* From the Sky Lake PRM Vol. 2d,
-       * RENDER_SURFACE_STATE::Shader Channel Select Red
-       *
-       *    "For Render Target, Red, Green and Blue Shader Channel Selects
-       *    MUST be such that only valid components can be swapped i.e. only
-       *    change the order of components in the pixel. Any other values for
-       *    these Shader Channel Select fields are not valid for Render
-       *    Targets. This also means that there MUST not be multiple shader
-       *    channels mapped to the same RT channel."
-       */
-      assert(info->view->swizzle.r == ISL_CHANNEL_SELECT_RED ||
-             info->view->swizzle.r == ISL_CHANNEL_SELECT_GREEN ||
-             info->view->swizzle.r == ISL_CHANNEL_SELECT_BLUE);
-      assert(info->view->swizzle.g == ISL_CHANNEL_SELECT_RED ||
-             info->view->swizzle.g == ISL_CHANNEL_SELECT_GREEN ||
-             info->view->swizzle.g == ISL_CHANNEL_SELECT_BLUE);
-      assert(info->view->swizzle.b == ISL_CHANNEL_SELECT_RED ||
-             info->view->swizzle.b == ISL_CHANNEL_SELECT_GREEN ||
-             info->view->swizzle.b == ISL_CHANNEL_SELECT_BLUE);
-      assert(info->view->swizzle.r != info->view->swizzle.g);
-      assert(info->view->swizzle.r != info->view->swizzle.b);
-      assert(info->view->swizzle.g != info->view->swizzle.b);
-
-      /* From the Sky Lake PRM Vol. 2d,
-       * RENDER_SURFACE_STATE::Shader Channel Select Alpha
-       *
-       *    "For Render Target, this field MUST be programmed to
-       *    value = SCS_ALPHA."
-       */
-      assert(info->view->swizzle.a == ISL_CHANNEL_SELECT_ALPHA);
-   }
-   s.ShaderChannelSelectRed = info->view->swizzle.r;
-   s.ShaderChannelSelectGreen = info->view->swizzle.g;
-   s.ShaderChannelSelectBlue = info->view->swizzle.b;
-   s.ShaderChannelSelectAlpha = info->view->swizzle.a;
+   if (info->view->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT)
+      assert(isl_swizzle_supports_rendering(dev->info, info->view->swizzle));
+
+   s.ShaderChannelSelectRed = (enum GENX(ShaderChannelSelect)) info->view->swizzle.r;
+   s.ShaderChannelSelectGreen = (enum GENX(ShaderChannelSelect)) info->view->swizzle.g;
+   s.ShaderChannelSelectBlue = (enum GENX(ShaderChannelSelect)) info->view->swizzle.b;
+   s.ShaderChannelSelectAlpha = (enum GENX(ShaderChannelSelect)) info->view->swizzle.a;
+#else
+   assert(isl_swizzle_is_identity(info->view->swizzle));
 #endif
 
    s.SurfaceBaseAddress = info->address;
@@ -640,11 +610,21 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state,
 #endif
 
    if (info->aux_usage != ISL_AUX_USAGE_NONE) {
+      if (info->use_clear_address) {
+#if GEN_GEN >= 10
+         s.ClearValueAddressEnable = true;
+         s.ClearValueAddress = info->clear_address;
+#else
+         unreachable("Gen9 and earlier do not support indirect clear colors");
+#endif
+      }
 #if GEN_GEN >= 9
-      s.RedClearColor = info->clear_color.u32[0];
-      s.GreenClearColor = info->clear_color.u32[1];
-      s.BlueClearColor = info->clear_color.u32[2];
-      s.AlphaClearColor = info->clear_color.u32[3];
+      if (!info->use_clear_address) {
+         s.RedClearColor = info->clear_color.u32[0];
+         s.GreenClearColor = info->clear_color.u32[1];
+         s.BlueClearColor = info->clear_color.u32[2];
+         s.AlphaClearColor = info->clear_color.u32[3];
+      }
 #elif GEN_GEN >= 7
       /* Prior to Sky Lake, we only have one bit for the clear color which
        * gives us 0 or 1 in whatever the surface's format happens to be.
@@ -678,7 +658,27 @@ void
 isl_genX(buffer_fill_state_s)(void *state,
                               const struct isl_buffer_fill_state_info *restrict info)
 {
-   uint32_t num_elements = info->size / info->stride;
+   uint64_t buffer_size = info->size;
+
+   /* Uniform and Storage buffers need to have surface size not less that the
+    * aligned 32-bit size of the buffer. To calculate the array lenght on
+    * unsized arrays in StorageBuffer the last 2 bits store the padding size
+    * added to the surface, so we can calculate latter the original buffer
+    * size to know the number of elements.
+    *
+    *  surface_size = isl_align(buffer_size, 4) +
+    *                 (isl_align(buffer_size) - buffer_size)
+    *
+    *  buffer_size = (surface_size & ~3) - (surface_size & 3)
+    */
+   if (info->format == ISL_FORMAT_RAW  ||
+       info->stride < isl_format_get_layout(info->format)->bpb / 8) {
+      assert(info->stride == 1);
+      uint64_t aligned_size = isl_align(buffer_size, 4);
+      buffer_size = aligned_size + (aligned_size - buffer_size);
+   }
+
+   uint32_t num_elements = buffer_size / info->stride;
 
    if (GEN_GEN >= 7) {
       /* From the IVB PRM, SURFACE_STATE::Height,
@@ -753,3 +753,29 @@ isl_genX(buffer_fill_state_s)(void *state,
 
    GENX(RENDER_SURFACE_STATE_pack)(NULL, state, &s);
 }
+
+void
+isl_genX(null_fill_state)(void *state, struct isl_extent3d size)
+{
+   struct GENX(RENDER_SURFACE_STATE) s = {
+      .SurfaceType = SURFTYPE_NULL,
+      .SurfaceFormat = ISL_FORMAT_B8G8R8A8_UNORM,
+#if GEN_GEN >= 7
+      .SurfaceArray = size.depth > 0,
+#endif
+#if GEN_GEN >= 8
+      .TileMode = YMAJOR,
+#else
+      .TiledSurface = true,
+      .TileWalk = TILEWALK_YMAJOR,
+#endif
+      .Width = size.width - 1,
+      .Height = size.height - 1,
+      .Depth = size.depth - 1,
+      .RenderTargetViewExtent = size.depth - 1,
+#if GEN_GEN <= 5
+      .ColorBufferComponentWriteDisables = 0xf,
+#endif
+   };
+   GENX(RENDER_SURFACE_STATE_pack)(NULL, state, &s);
+}