intel/gpu_dump: fix argument passing

[mesa.git] / src / intel / tools / aubinator_error_decode.c

diff --git a/src/intel/tools/aubinator_error_decode.c b/src/intel/tools/aubinator_error_decode.c
index c581414eb2cdc5e0a9dd95f8d104cbd7faf8d97c..049823ca46326f2f4d7c64a83c8e0d9efd131d21 100644 (file)
--- a/src/intel/tools/aubinator_error_decode.c
+++ b/src/intel/tools/aubinator_error_decode.c
@@ -76,49 +76,42 @@ print_register(struct gen_spec *spec, const char *name, uint32_t reg)
 }
 
 struct ring_register_mapping {
-   unsigned ring_class;
+   enum drm_i915_gem_engine_class ring_class;
    unsigned ring_instance;
    const char *register_name;
 };
 
-enum {
-   RCS,
-   BCS,
-   VCS,
-   VECS,
-};
-
 static const struct ring_register_mapping acthd_registers[] = {
-   { BCS, 0, "BCS_ACTHD_UDW" },
-   { VCS, 0, "VCS_ACTHD_UDW" },
-   { VCS, 1, "VCS2_ACTHD_UDW" },
-   { RCS, 0, "ACTHD_UDW" },
-   { VECS, 0, "VECS_ACTHD_UDW" },
+   { I915_ENGINE_CLASS_COPY, 0, "BCS_ACTHD_UDW" },
+   { I915_ENGINE_CLASS_VIDEO, 0, "VCS_ACTHD_UDW" },
+   { I915_ENGINE_CLASS_VIDEO, 1, "VCS2_ACTHD_UDW" },
+   { I915_ENGINE_CLASS_RENDER, 0, "ACTHD_UDW" },
+   { I915_ENGINE_CLASS_VIDEO_ENHANCE, 0, "VECS_ACTHD_UDW" },
 };
 
 static const struct ring_register_mapping ctl_registers[] = {
-   { BCS, 0, "BCS_RING_BUFFER_CTL" },
-   { VCS, 0, "VCS_RING_BUFFER_CTL" },
-   { VCS, 1, "VCS2_RING_BUFFER_CTL" },
-   { RCS, 0, "RCS_RING_BUFFER_CTL" },
-   { VECS, 0,  "VECS_RING_BUFFER_CTL" },
+   { I915_ENGINE_CLASS_COPY, 0, "BCS_RING_BUFFER_CTL" },
+   { I915_ENGINE_CLASS_VIDEO, 0, "VCS_RING_BUFFER_CTL" },
+   { I915_ENGINE_CLASS_VIDEO, 1, "VCS2_RING_BUFFER_CTL" },
+   { I915_ENGINE_CLASS_RENDER, 0, "RCS_RING_BUFFER_CTL" },
+   { I915_ENGINE_CLASS_VIDEO_ENHANCE, 0,  "VECS_RING_BUFFER_CTL" },
 };
 
 static const struct ring_register_mapping fault_registers[] = {
-   { BCS, 0, "BCS_FAULT_REG" },
-   { VCS, 0, "VCS_FAULT_REG" },
-   { RCS, 0, "RCS_FAULT_REG" },
-   { VECS, 0, "VECS_FAULT_REG" },
+   { I915_ENGINE_CLASS_COPY, 0, "BCS_FAULT_REG" },
+   { I915_ENGINE_CLASS_VIDEO, 0, "VCS_FAULT_REG" },
+   { I915_ENGINE_CLASS_RENDER, 0, "RCS_FAULT_REG" },
+   { I915_ENGINE_CLASS_VIDEO_ENHANCE, 0, "VECS_FAULT_REG" },
 };
 
 static int ring_name_to_class(const char *ring_name,
-                              unsigned int *class)
+                              enum drm_i915_gem_engine_class *class)
 {
    static const char *class_names[] = {
-      [RCS] = "rcs",
-      [BCS] = "bcs",
-      [VCS] = "vcs",
-      [VECS] = "vecs",
+      [I915_ENGINE_CLASS_RENDER] = "rcs",
+      [I915_ENGINE_CLASS_COPY] = "bcs",
+      [I915_ENGINE_CLASS_VIDEO] = "vcs",
+      [I915_ENGINE_CLASS_VIDEO_ENHANCE] = "vecs",
    };
    for (size_t i = 0; i < ARRAY_SIZE(class_names); i++) {
       if (strncmp(ring_name, class_names[i], strlen(class_names[i])))
@@ -133,11 +126,11 @@ static int ring_name_to_class(const char *ring_name,
       unsigned int class;
       int instance;
    } legacy_names[] = {
-      { "render", RCS, 0 },
-      { "blt", BCS, 0 },
-      { "bsd", VCS, 0 },
-      { "bsd2", VCS, 1 },
-      { "vebox", VECS, 0 },
+      { "render", I915_ENGINE_CLASS_RENDER, 0 },
+      { "blt", I915_ENGINE_CLASS_COPY, 0 },
+      { "bsd", I915_ENGINE_CLASS_VIDEO, 0 },
+      { "bsd2", I915_ENGINE_CLASS_VIDEO, 1 },
+      { "vebox", I915_ENGINE_CLASS_VIDEO_ENHANCE, 0 },
    };
    for (size_t i = 0; i < ARRAY_SIZE(legacy_names); i++) {
       if (strcmp(ring_name, legacy_names[i].name))
@@ -155,7 +148,7 @@ register_name_from_ring(const struct ring_register_mapping *mapping,
                         unsigned nb_mapping,
                         const char *ring_name)
 {
-   unsigned int class;
+   enum drm_i915_gem_engine_class class;
    int instance;
 
    instance = ring_name_to_class(ring_name, &class);
@@ -174,7 +167,7 @@ static const char *
 instdone_register_for_ring(const struct gen_device_info *devinfo,
                            const char *ring_name)
 {
-   unsigned int class;
+   enum drm_i915_gem_engine_class class;
    int instance;
 
    instance = ring_name_to_class(ring_name, &class);
@@ -182,16 +175,16 @@ instdone_register_for_ring(const struct gen_device_info *devinfo,
       return NULL;
 
    switch (class) {
-   case RCS:
+   case I915_ENGINE_CLASS_RENDER:
       if (devinfo->gen == 6)
          return "INSTDONE_2";
       else
          return "INSTDONE_1";
 
-   case BCS:
+   case I915_ENGINE_CLASS_COPY:
       return "BCS_INSTDONE";
 
-   case VCS:
+   case I915_ENGINE_CLASS_VIDEO:
       switch (instance) {
       case 0:
          return "VCS_INSTDONE";
@@ -201,8 +194,11 @@ instdone_register_for_ring(const struct gen_device_info *devinfo,
          return NULL;
       }
 
-   case VECS:
+   case I915_ENGINE_CLASS_VIDEO_ENHANCE:
       return "VECS_INSTDONE";
+
+   default:
+      return NULL;
    }
 
    return NULL;
@@ -385,7 +381,7 @@ static int ascii85_decode(const char *in, uint32_t **out, bool inflate)
 }
 
 static struct gen_batch_decode_bo
-get_gen_batch_bo(void *user_data, uint64_t address)
+get_gen_batch_bo(void *user_data, bool ppgtt, uint64_t address)
 {
    for (int s = 0; s < num_sections; s++) {
       if (sections[s].gtt_offset <= address &&
@@ -601,6 +597,9 @@ read_data_file(FILE *file)
 
 
    for (int s = 0; s < num_sections; s++) {
+      enum drm_i915_gem_engine_class class;
+      ring_name_to_class(sections[s].ring_name, &class);
+
       printf("--- %s (%s) at 0x%08x %08x\n",
              sections[s].buffer_name, sections[s].ring_name,
              (unsigned) (sections[s].gtt_offset >> 32),
@@ -610,9 +609,10 @@ read_data_file(FILE *file)
           strcmp(sections[s].buffer_name, "batch buffer") == 0 ||
           strcmp(sections[s].buffer_name, "ring buffer") == 0 ||
           strcmp(sections[s].buffer_name, "HW Context") == 0) {
+         batch_ctx.engine = class;
          gen_print_batch(&batch_ctx, sections[s].data,
                          sections[s].dword_count * 4,
-                         sections[s].gtt_offset);
+                         sections[s].gtt_offset, false);
       }
    }