return true;
}
-static void
+static bool
upload_blorp_shader(struct blorp_context *blorp,
const void *key, uint32_t key_size,
const void *kernel, uint32_t kernel_size,
key, key_size, kernel, kernel_size,
prog_data, prog_data_size, &bind_map);
+ if (!bin)
+ return false;
+
/* The cache already has a reference and it's not going anywhere so there
* is no need to hold a second reference.
*/
*kernel_out = bin->kernel.offset;
*(const struct brw_stage_prog_data **)prog_data_out = bin->prog_data;
+
+ return true;
}
void
case 9:
device->blorp.exec = gen9_blorp_exec;
break;
+ case 10:
+ device->blorp.exec = gen10_blorp_exec;
+ break;
default:
unreachable("Unknown hardware generation");
}
{
const struct isl_format_layout *fmtl =
isl_format_get_layout(format);
+ bool ok UNUSED;
/* ASTC is the only format which doesn't support linear layouts.
* Create an equivalently sized surface with ISL to get around this.
},
};
- isl_surf_init(&device->isl_dev, isl_surf,
- .dim = ISL_SURF_DIM_2D,
- .format = format,
- .width = width,
- .height = height,
- .depth = 1,
- .levels = 1,
- .array_len = 1,
- .samples = 1,
- .min_pitch = row_pitch,
- .usage = ISL_SURF_USAGE_TEXTURE_BIT |
- ISL_SURF_USAGE_RENDER_TARGET_BIT,
- .tiling_flags = ISL_TILING_LINEAR_BIT);
- assert(isl_surf->row_pitch == row_pitch);
+ ok = isl_surf_init(&device->isl_dev, isl_surf,
+ .dim = ISL_SURF_DIM_2D,
+ .format = format,
+ .width = width,
+ .height = height,
+ .depth = 1,
+ .levels = 1,
+ .array_len = 1,
+ .samples = 1,
+ .row_pitch = row_pitch,
+ .usage = ISL_SURF_USAGE_TEXTURE_BIT |
+ ISL_SURF_USAGE_RENDER_TARGET_BIT,
+ .tiling_flags = ISL_TILING_LINEAR_BIT);
+ assert(ok);
}
static void
layer_count = pRegions[r].extent.depth;
} else {
dst_base_layer = pRegions[r].dstSubresource.baseArrayLayer;
- layer_count = pRegions[r].dstSubresource.layerCount;
+ layer_count =
+ anv_get_layerCount(dst_image, &pRegions[r].dstSubresource);
}
unsigned src_base_layer;
src_base_layer = pRegions[r].srcOffset.z;
} else {
src_base_layer = pRegions[r].srcSubresource.baseArrayLayer;
- assert(pRegions[r].srcSubresource.layerCount == layer_count);
+ assert(layer_count ==
+ anv_get_layerCount(src_image, &pRegions[r].srcSubresource));
}
assert(pRegions[r].srcSubresource.aspectMask ==
anv_sanitize_image_extent(anv_image->type, pRegions[r].imageExtent);
if (anv_image->type != VK_IMAGE_TYPE_3D) {
image.offset.z = pRegions[r].imageSubresource.baseArrayLayer;
- extent.depth = pRegions[r].imageSubresource.layerCount;
+ extent.depth =
+ anv_get_layerCount(anv_image, &pRegions[r].imageSubresource);
}
const enum isl_format buffer_format =
dst_end = pRegions[r].dstOffsets[1].z;
} else {
dst_start = dst_res->baseArrayLayer;
- dst_end = dst_start + dst_res->layerCount;
+ dst_end = dst_start + anv_get_layerCount(dst_image, dst_res);
}
unsigned src_start, src_end;
src_end = pRegions[r].srcOffsets[1].z;
} else {
src_start = src_res->baseArrayLayer;
- src_end = src_start + src_res->layerCount;
+ src_end = src_start + anv_get_layerCount(src_image, src_res);
}
bool flip_z = flip_coords(&src_start, &src_end, &dst_start, &dst_end);
* little data at the top to build its linked list.
*/
const uint32_t max_update_size =
- cmd_buffer->device->dynamic_state_block_pool.block_size - 64;
+ cmd_buffer->device->dynamic_state_pool.block_size - 64;
assert(max_update_size < MAX_SURFACE_DIM * 4);
+ /* We're about to read data that was written from the CPU. Flush the
+ * texture cache so we don't get anything stale.
+ */
+ cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT;
+
while (dataSize) {
const uint32_t copy_size = MIN2(dataSize, max_update_size);
memcpy(tmp_data.map, pData, copy_size);
+ anv_state_flush(cmd_buffer->device, tmp_data);
+
int bs = 16;
bs = gcd_pow2_u64(bs, dstOffset);
bs = gcd_pow2_u64(bs, copy_size);
do_buffer_copy(&batch,
- &cmd_buffer->device->dynamic_state_block_pool.bo,
+ &cmd_buffer->device->dynamic_state_pool.block_pool.bo,
tmp_data.offset,
dst_buffer->bo, dst_buffer->offset + dstOffset,
copy_size / bs, 1, bs);
struct blorp_batch batch;
blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
- if (fillSize == VK_WHOLE_SIZE) {
- fillSize = dst_buffer->size - dstOffset;
- /* Make sure fillSize is a multiple of 4 */
- fillSize &= ~3ull;
- }
+ fillSize = anv_buffer_get_range(dst_buffer, dstOffset, fillSize);
+
+ /* From the Vulkan spec:
+ *
+ * "size is the number of bytes to fill, and must be either a multiple
+ * of 4, or VK_WHOLE_SIZE to fill the range from offset to the end of
+ * the buffer. If VK_WHOLE_SIZE is used and the remaining size of the
+ * buffer is not a multiple of 4, then the nearest smaller multiple is
+ * used."
+ */
+ fillSize &= ~3ull;
/* First, we compute the biggest format that can be used with the
* given offsets and size.
VK_IMAGE_ASPECT_COLOR_BIT, image->tiling);
unsigned base_layer = pRanges[r].baseArrayLayer;
- unsigned layer_count = pRanges[r].layerCount;
+ unsigned layer_count = anv_get_layerCount(image, &pRanges[r]);
for (unsigned i = 0; i < anv_get_levelCount(image, &pRanges[r]); i++) {
const unsigned level = pRanges[r].baseMipLevel + i;
}
blorp_clear(&batch, &surf,
- src_format.isl_format,
- anv_swizzle_for_render(src_format.swizzle),
+ src_format.isl_format, src_format.swizzle,
level, base_layer, layer_count,
0, 0, level_width, level_height,
vk_to_isl_color(*pColor), color_write_disable);
bool clear_stencil = pRanges[r].aspectMask & VK_IMAGE_ASPECT_STENCIL_BIT;
unsigned base_layer = pRanges[r].baseArrayLayer;
- unsigned layer_count = pRanges[r].layerCount;
+ unsigned layer_count = anv_get_layerCount(image, &pRanges[r]);
for (unsigned i = 0; i < anv_get_levelCount(image, &pRanges[r]); i++) {
const unsigned level = pRanges[r].baseMipLevel + i;
blorp_batch_finish(&batch);
}
-struct anv_state
+VkResult
anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer *cmd_buffer,
uint32_t num_entries,
- uint32_t *state_offset)
+ uint32_t *state_offset,
+ struct anv_state *bt_state)
{
- struct anv_state bt_state =
- anv_cmd_buffer_alloc_binding_table(cmd_buffer, num_entries,
- state_offset);
- if (bt_state.map == NULL) {
+ *bt_state = anv_cmd_buffer_alloc_binding_table(cmd_buffer, num_entries,
+ state_offset);
+ if (bt_state->map == NULL) {
/* We ran out of space. Grab a new binding table block. */
- MAYBE_UNUSED VkResult result =
- anv_cmd_buffer_new_binding_table_block(cmd_buffer);
- assert(result == VK_SUCCESS);
+ VkResult result = anv_cmd_buffer_new_binding_table_block(cmd_buffer);
+ if (result != VK_SUCCESS)
+ return result;
/* Re-emit state base addresses so we get the new surface state base
* address before we start emitting binding tables etc.
*/
anv_cmd_buffer_emit_state_base_address(cmd_buffer);
- bt_state = anv_cmd_buffer_alloc_binding_table(cmd_buffer, num_entries,
- state_offset);
- assert(bt_state.map != NULL);
+ *bt_state = anv_cmd_buffer_alloc_binding_table(cmd_buffer, num_entries,
+ state_offset);
+ assert(bt_state->map != NULL);
}
- return bt_state;
+ return VK_SUCCESS;
}
-static uint32_t
+static VkResult
binding_table_for_surface_state(struct anv_cmd_buffer *cmd_buffer,
- struct anv_state surface_state)
+ struct anv_state surface_state,
+ uint32_t *bt_offset)
{
uint32_t state_offset;
- struct anv_state bt_state =
- anv_cmd_buffer_alloc_blorp_binding_table(cmd_buffer, 1, &state_offset);
+ struct anv_state bt_state;
+
+ VkResult result =
+ anv_cmd_buffer_alloc_blorp_binding_table(cmd_buffer, 1, &state_offset,
+ &bt_state);
+ if (result != VK_SUCCESS)
+ return result;
uint32_t *bt_map = bt_state.map;
bt_map[0] = surface_state.offset + state_offset;
- return bt_state.offset;
+ *bt_offset = bt_state.offset;
+ return VK_SUCCESS;
}
static void
{
const struct anv_subpass *subpass = cmd_buffer->state.subpass;
const uint32_t color_att = attachment->colorAttachment;
- const uint32_t att_idx = subpass->color_attachments[color_att];
+ const uint32_t att_idx = subpass->color_attachments[color_att].attachment;
if (att_idx == VK_ATTACHMENT_UNUSED)
return;
struct anv_attachment_state *att_state =
&cmd_buffer->state.attachments[att_idx];
- uint32_t binding_table =
- binding_table_for_surface_state(cmd_buffer, att_state->color_rt_state);
+ uint32_t binding_table;
+ VkResult result =
+ binding_table_for_surface_state(cmd_buffer, att_state->color_rt_state,
+ &binding_table);
+ if (result != VK_SUCCESS)
+ return;
union isl_color_value clear_color =
vk_to_isl_color(attachment->clearValue.color);
+ /* If multiview is enabled we ignore baseArrayLayer and layerCount */
+ if (subpass->view_mask) {
+ uint32_t view_idx;
+ for_each_bit(view_idx, subpass->view_mask) {
+ for (uint32_t r = 0; r < rectCount; ++r) {
+ const VkOffset2D offset = pRects[r].rect.offset;
+ const VkExtent2D extent = pRects[r].rect.extent;
+ blorp_clear_attachments(batch, binding_table,
+ ISL_FORMAT_UNSUPPORTED, pass_att->samples,
+ view_idx, 1,
+ offset.x, offset.y,
+ offset.x + extent.width,
+ offset.y + extent.height,
+ true, clear_color, false, 0.0f, 0, 0);
+ }
+ }
+ return;
+ }
+
for (uint32_t r = 0; r < rectCount; ++r) {
const VkOffset2D offset = pRects[r].rect.offset;
const VkExtent2D extent = pRects[r].rect.extent;
{
static const union isl_color_value color_value = { .u32 = { 0, } };
const struct anv_subpass *subpass = cmd_buffer->state.subpass;
- const uint32_t att_idx = subpass->depth_stencil_attachment;
+ const uint32_t att_idx = subpass->depth_stencil_attachment.attachment;
if (att_idx == VK_ATTACHMENT_UNUSED)
return;
VK_IMAGE_TILING_OPTIMAL);
}
- uint32_t binding_table =
+ uint32_t binding_table;
+ VkResult result =
binding_table_for_surface_state(cmd_buffer,
- cmd_buffer->state.null_surface_state);
+ cmd_buffer->state.null_surface_state,
+ &binding_table);
+ if (result != VK_SUCCESS)
+ return;
+
+ /* If multiview is enabled we ignore baseArrayLayer and layerCount */
+ if (subpass->view_mask) {
+ uint32_t view_idx;
+ for_each_bit(view_idx, subpass->view_mask) {
+ for (uint32_t r = 0; r < rectCount; ++r) {
+ const VkOffset2D offset = pRects[r].rect.offset;
+ const VkExtent2D extent = pRects[r].rect.extent;
+ VkClearDepthStencilValue value = attachment->clearValue.depthStencil;
+ blorp_clear_attachments(batch, binding_table,
+ depth_format, pass_att->samples,
+ view_idx, 1,
+ offset.x, offset.y,
+ offset.x + extent.width,
+ offset.y + extent.height,
+ false, color_value,
+ clear_depth, value.depth,
+ clear_stencil ? 0xff : 0, value.stencil);
+ }
+ }
+ return;
+ }
for (uint32_t r = 0; r < rectCount; ++r) {
const VkOffset2D offset = pRects[r].rect.offset;
SUBPASS_STAGE_RESOLVE,
};
-static bool
-attachment_needs_flush(struct anv_cmd_buffer *cmd_buffer,
- struct anv_render_pass_attachment *att,
- enum subpass_stage stage)
-{
- struct anv_render_pass *pass = cmd_buffer->state.pass;
- struct anv_subpass *subpass = cmd_buffer->state.subpass;
- unsigned subpass_idx = subpass - pass->subpasses;
- assert(subpass_idx < pass->subpass_count);
-
- /* We handle this subpass specially based on the current stage */
- enum anv_subpass_usage usage = att->subpass_usage[subpass_idx];
- switch (stage) {
- case SUBPASS_STAGE_LOAD:
- if (usage & (ANV_SUBPASS_USAGE_INPUT | ANV_SUBPASS_USAGE_RESOLVE_SRC))
- return true;
- break;
-
- case SUBPASS_STAGE_DRAW:
- if (usage & ANV_SUBPASS_USAGE_RESOLVE_SRC)
- return true;
- break;
-
- default:
- break;
- }
-
- for (uint32_t s = subpass_idx + 1; s < pass->subpass_count; s++) {
- usage = att->subpass_usage[s];
-
- /* If this attachment is going to be used as an input in this or any
- * future subpass, then we need to flush its cache and invalidate the
- * texture cache.
- */
- if (att->subpass_usage[s] & ANV_SUBPASS_USAGE_INPUT)
- return true;
-
- if (usage & (ANV_SUBPASS_USAGE_DRAW | ANV_SUBPASS_USAGE_RESOLVE_DST)) {
- /* We found another subpass that draws to this attachment. We'll
- * wait to resolve until then.
- */
- return false;
- }
- }
-
- return false;
-}
-
-static void
-anv_cmd_buffer_flush_attachments(struct anv_cmd_buffer *cmd_buffer,
- enum subpass_stage stage)
-{
- struct anv_subpass *subpass = cmd_buffer->state.subpass;
- struct anv_render_pass *pass = cmd_buffer->state.pass;
-
- for (uint32_t i = 0; i < subpass->color_count; ++i) {
- uint32_t att = subpass->color_attachments[i];
- assert(att < pass->attachment_count);
- if (attachment_needs_flush(cmd_buffer, &pass->attachments[att], stage)) {
- cmd_buffer->state.pending_pipe_bits |=
- ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT |
- ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT;
- }
- }
-
- if (subpass->depth_stencil_attachment != VK_ATTACHMENT_UNUSED) {
- uint32_t att = subpass->depth_stencil_attachment;
- assert(att < pass->attachment_count);
- if (attachment_needs_flush(cmd_buffer, &pass->attachments[att], stage)) {
- cmd_buffer->state.pending_pipe_bits |=
- ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT |
- ANV_PIPE_DEPTH_CACHE_FLUSH_BIT;
- }
- }
-}
-
static bool
subpass_needs_clear(const struct anv_cmd_buffer *cmd_buffer)
{
const struct anv_cmd_state *cmd_state = &cmd_buffer->state;
- uint32_t ds = cmd_state->subpass->depth_stencil_attachment;
+ uint32_t ds = cmd_state->subpass->depth_stencil_attachment.attachment;
for (uint32_t i = 0; i < cmd_state->subpass->color_count; ++i) {
- uint32_t a = cmd_state->subpass->color_attachments[i];
+ uint32_t a = cmd_state->subpass->color_attachments[i].attachment;
+ if (a == VK_ATTACHMENT_UNUSED)
+ continue;
+
+ assert(a < cmd_state->pass->attachment_count);
if (cmd_state->attachments[a].pending_clear_aspects) {
return true;
}
}
- if (ds != VK_ATTACHMENT_UNUSED &&
- cmd_state->attachments[ds].pending_clear_aspects) {
- return true;
+ if (ds != VK_ATTACHMENT_UNUSED) {
+ assert(ds < cmd_state->pass->attachment_count);
+ if (cmd_state->attachments[ds].pending_clear_aspects)
+ return true;
}
return false;
struct anv_framebuffer *fb = cmd_buffer->state.framebuffer;
for (uint32_t i = 0; i < cmd_state->subpass->color_count; ++i) {
- const uint32_t a = cmd_state->subpass->color_attachments[i];
+ const uint32_t a = cmd_state->subpass->color_attachments[i].attachment;
+ if (a == VK_ATTACHMENT_UNUSED)
+ continue;
+
+ assert(a < cmd_state->pass->attachment_count);
struct anv_attachment_state *att_state = &cmd_state->attachments[a];
if (!att_state->pending_clear_aspects)
struct blorp_surf surf;
get_blorp_surf_for_anv_image(image, VK_IMAGE_ASPECT_COLOR_BIT,
att_state->aux_usage, &surf);
- surf.clear_color = vk_to_isl_color(att_state->clear_value.color);
if (att_state->fast_clear) {
- blorp_fast_clear(&batch, &surf, iview->isl.format,
- iview->isl.base_level,
- iview->isl.base_array_layer, fb->layers,
- render_area.offset.x, render_area.offset.y,
- render_area.offset.x + render_area.extent.width,
- render_area.offset.y + render_area.extent.height);
+ surf.clear_color = vk_to_isl_color(att_state->clear_value.color);
/* From the Sky Lake PRM Vol. 7, "Render Target Fast Clear":
*
* "After Render target fast clear, pipe-control with color cache
* write-flush must be issued before sending any DRAW commands on
* that render target."
+ *
+ * This comment is a bit cryptic and doesn't really tell you what's
+ * going or what's really needed. It appears that fast clear ops are
+ * not properly synchronized with other drawing. This means that we
+ * cannot have a fast clear operation in the pipe at the same time as
+ * other regular drawing operations. We need to use a PIPE_CONTROL
+ * to ensure that the contents of the previous draw hit the render
+ * target before we resolve and then use a second PIPE_CONTROL after
+ * the resolve to ensure that it is completed before any additional
+ * drawing occurs.
*/
cmd_buffer->state.pending_pipe_bits |=
ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_CS_STALL_BIT;
+
+ blorp_fast_clear(&batch, &surf, iview->isl.format,
+ iview->isl.base_level,
+ iview->isl.base_array_layer, fb->layers,
+ render_area.offset.x, render_area.offset.y,
+ render_area.offset.x + render_area.extent.width,
+ render_area.offset.y + render_area.extent.height);
+
+ cmd_buffer->state.pending_pipe_bits |=
+ ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_CS_STALL_BIT;
} else {
blorp_clear(&batch, &surf, iview->isl.format,
anv_swizzle_for_render(iview->isl.swizzle),
render_area.offset.x, render_area.offset.y,
render_area.offset.x + render_area.extent.width,
render_area.offset.y + render_area.extent.height,
- surf.clear_color, NULL);
+ vk_to_isl_color(att_state->clear_value.color), NULL);
}
att_state->pending_clear_aspects = 0;
}
- const uint32_t ds = cmd_state->subpass->depth_stencil_attachment;
+ const uint32_t ds = cmd_state->subpass->depth_stencil_attachment.attachment;
+ assert(ds == VK_ATTACHMENT_UNUSED || ds < cmd_state->pass->attachment_count);
if (ds != VK_ATTACHMENT_UNUSED &&
cmd_state->attachments[ds].pending_clear_aspects) {
*/
clear_with_hiz = false;
} else if (gen == 8 &&
- anv_can_sample_with_hiz(cmd_buffer->device->info.gen,
+ anv_can_sample_with_hiz(&cmd_buffer->device->info,
+ iview->aspect_mask,
iview->image->samples)) {
/* Only gen9+ supports returning ANV_HZ_FC_VAL when sampling a
* fast-cleared portion of a HiZ buffer. Testing has revealed
clear_depth, clear_stencil,
clear_att.clearValue.
depthStencil.stencil);
+
+ /* From the SKL PRM, Depth Buffer Clear:
+ *
+ * Depth Buffer Clear Workaround
+ * Depth buffer clear pass using any of the methods (WM_STATE,
+ * 3DSTATE_WM or 3DSTATE_WM_HZ_OP) must be followed by a
+ * PIPE_CONTROL command with DEPTH_STALL bit and Depth FLUSH bits
+ * “set” before starting to render. DepthStall and DepthFlush are
+ * not needed between consecutive depth clear passes nor is it
+ * required if the depth-clear pass was done with “full_surf_clear”
+ * bit set in the 3DSTATE_WM_HZ_OP.
+ */
+ if (clear_depth) {
+ cmd_buffer->state.pending_pipe_bits |=
+ ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | ANV_PIPE_DEPTH_STALL_BIT;
+ }
}
}
}
blorp_batch_finish(&batch);
-
- anv_cmd_buffer_flush_attachments(cmd_buffer, SUBPASS_STAGE_LOAD);
}
static void
for (uint32_t r = 0; r < regionCount; r++) {
assert(pRegions[r].srcSubresource.aspectMask ==
pRegions[r].dstSubresource.aspectMask);
- assert(pRegions[r].srcSubresource.layerCount ==
- pRegions[r].dstSubresource.layerCount);
+ assert(anv_get_layerCount(src_image, &pRegions[r].srcSubresource) ==
+ anv_get_layerCount(dst_image, &pRegions[r].dstSubresource));
- const uint32_t layer_count = pRegions[r].dstSubresource.layerCount;
+ const uint32_t layer_count =
+ anv_get_layerCount(dst_image, &pRegions[r].dstSubresource);
for (uint32_t layer = 0; layer < layer_count; layer++) {
resolve_image(&batch,
blorp_batch_finish(&batch);
}
+void
+anv_image_ccs_clear(struct anv_cmd_buffer *cmd_buffer,
+ const struct anv_image *image,
+ const uint32_t base_level, const uint32_t level_count,
+ const uint32_t base_layer, uint32_t layer_count)
+{
+ assert(image->type == VK_IMAGE_TYPE_3D || image->extent.depth == 1);
+
+ if (image->type == VK_IMAGE_TYPE_3D) {
+ assert(base_layer == 0);
+ assert(layer_count == anv_minify(image->extent.depth, base_level));
+ }
+
+ struct blorp_batch batch;
+ blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
+
+ struct blorp_surf surf;
+ get_blorp_surf_for_anv_image(image, VK_IMAGE_ASPECT_COLOR_BIT,
+ image->aux_usage, &surf);
+
+ /* From the Sky Lake PRM Vol. 7, "Render Target Fast Clear":
+ *
+ * "After Render target fast clear, pipe-control with color cache
+ * write-flush must be issued before sending any DRAW commands on
+ * that render target."
+ *
+ * This comment is a bit cryptic and doesn't really tell you what's going
+ * or what's really needed. It appears that fast clear ops are not
+ * properly synchronized with other drawing. This means that we cannot
+ * have a fast clear operation in the pipe at the same time as other
+ * regular drawing operations. We need to use a PIPE_CONTROL to ensure
+ * that the contents of the previous draw hit the render target before we
+ * resolve and then use a second PIPE_CONTROL after the resolve to ensure
+ * that it is completed before any additional drawing occurs.
+ */
+ cmd_buffer->state.pending_pipe_bits |=
+ ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_CS_STALL_BIT;
+
+ for (uint32_t l = 0; l < level_count; l++) {
+ const uint32_t level = base_level + l;
+
+ const VkExtent3D extent = {
+ .width = anv_minify(image->extent.width, level),
+ .height = anv_minify(image->extent.height, level),
+ .depth = anv_minify(image->extent.depth, level),
+ };
+
+ if (image->type == VK_IMAGE_TYPE_3D)
+ layer_count = extent.depth;
+
+ assert(level < anv_image_aux_levels(image));
+ assert(base_layer + layer_count <= anv_image_aux_layers(image, level));
+ blorp_fast_clear(&batch, &surf, surf.surf->format,
+ level, base_layer, layer_count,
+ 0, 0, extent.width, extent.height);
+ }
+
+ cmd_buffer->state.pending_pipe_bits |=
+ ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_CS_STALL_BIT;
+}
+
static void
ccs_resolve_attachment(struct anv_cmd_buffer *cmd_buffer,
struct blorp_batch *batch,
struct anv_attachment_state *att_state =
&cmd_buffer->state.attachments[att];
- if (att_state->aux_usage == ISL_AUX_USAGE_NONE)
+ if (att_state->aux_usage == ISL_AUX_USAGE_NONE ||
+ att_state->aux_usage == ISL_AUX_USAGE_MCS)
return; /* Nothing to resolve */
assert(att_state->aux_usage == ISL_AUX_USAGE_CCS_E ||
att_state->aux_usage == ISL_AUX_USAGE_CCS_D);
struct anv_render_pass *pass = cmd_buffer->state.pass;
- struct anv_subpass *subpass = cmd_buffer->state.subpass;
- unsigned subpass_idx = subpass - pass->subpasses;
- assert(subpass_idx < pass->subpass_count);
+ const uint32_t subpass_idx = anv_get_subpass_id(&cmd_buffer->state);
/* Scan forward to see what all ways this attachment will be used.
* Ideally, we would like to resolve in the same subpass as the last write
resolve_op = BLORP_FAST_CLEAR_OP_RESOLVE_FULL;
} else if (att_state->fast_clear) {
/* We don't know what to do with clear colors outside the render
- * pass. We need a partial resolve.
+ * pass. We need a partial resolve. Only transparent black is
+ * built into the surface state object and thus no resolve is
+ * required for this case.
*/
- resolve_op = BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL;
+ if (att_state->clear_value.color.uint32[0] ||
+ att_state->clear_value.color.uint32[1] ||
+ att_state->clear_value.color.uint32[2] ||
+ att_state->clear_value.color.uint32[3])
+ resolve_op = BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL;
} else {
/* The image "natively" supports all the compression we care about
* and we don't need to resolve at all. If this is the case, we also
struct blorp_surf surf;
get_blorp_surf_for_anv_image(image, VK_IMAGE_ASPECT_COLOR_BIT,
att_state->aux_usage, &surf);
- surf.clear_color = vk_to_isl_color(att_state->clear_value.color);
+ if (att_state->fast_clear)
+ surf.clear_color = vk_to_isl_color(att_state->clear_value.color);
/* From the Sky Lake PRM Vol. 7, "Render Target Resolve":
*
/* Once we've done any sort of resolve, we're no longer fast-cleared */
att_state->fast_clear = false;
+ if (att_state->aux_usage == ISL_AUX_USAGE_CCS_D)
+ att_state->aux_usage = ISL_AUX_USAGE_NONE;
}
void
blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
for (uint32_t i = 0; i < subpass->color_count; ++i) {
- ccs_resolve_attachment(cmd_buffer, &batch,
- subpass->color_attachments[i]);
- }
+ const uint32_t att = subpass->color_attachments[i].attachment;
+ if (att == VK_ATTACHMENT_UNUSED)
+ continue;
- anv_cmd_buffer_flush_attachments(cmd_buffer, SUBPASS_STAGE_DRAW);
+ assert(att < cmd_buffer->state.pass->attachment_count);
+ ccs_resolve_attachment(cmd_buffer, &batch, att);
+ }
if (subpass->has_resolve) {
+ /* We are about to do some MSAA resolves. We need to flush so that the
+ * result of writes to the MSAA color attachments show up in the sampler
+ * when we blit to the single-sampled resolve target.
+ */
+ cmd_buffer->state.pending_pipe_bits |=
+ ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT |
+ ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT;
+
for (uint32_t i = 0; i < subpass->color_count; ++i) {
- uint32_t src_att = subpass->color_attachments[i];
- uint32_t dst_att = subpass->resolve_attachments[i];
+ uint32_t src_att = subpass->color_attachments[i].attachment;
+ uint32_t dst_att = subpass->resolve_attachments[i].attachment;
if (dst_att == VK_ATTACHMENT_UNUSED)
continue;
+ assert(src_att < cmd_buffer->state.pass->attachment_count);
+ assert(dst_att < cmd_buffer->state.pass->attachment_count);
+
if (cmd_buffer->state.attachments[dst_att].pending_clear_aspects) {
/* From the Vulkan 1.0 spec:
*
ccs_resolve_attachment(cmd_buffer, &batch, dst_att);
}
-
- anv_cmd_buffer_flush_attachments(cmd_buffer, SUBPASS_STAGE_RESOLVE);
}
blorp_batch_finish(&batch);
};
surf.aux_usage = ISL_AUX_USAGE_HIZ;
- surf.clear_color.u32[0] = (uint32_t) ANV_HZ_FC_VAL;
+ surf.clear_color.f32[0] = ANV_HZ_FC_VAL;
- blorp_gen6_hiz_op(&batch, &surf, 0, 0, op);
+ blorp_hiz_op(&batch, &surf, 0, 0, 1, op);
blorp_batch_finish(&batch);
}
projects / mesa.git / blobdiff