anv_pipeline_cache_init(&device->blorp_shader_cache, device, true);
blorp_init(&device->blorp, device, &device->isl_dev);
device->blorp.compiler = device->instance->physicalDevice.compiler;
- device->blorp.mocs.tex = device->default_mocs;
- device->blorp.mocs.rb = device->default_mocs;
- device->blorp.mocs.vb = device->default_mocs;
device->blorp.lookup_shader = lookup_blorp_shader;
device->blorp.upload_shader = upload_blorp_shader;
switch (device->info.gen) {
case 9:
device->blorp.exec = gen9_blorp_exec;
break;
+ case 10:
+ device->blorp.exec = gen10_blorp_exec;
+ break;
default:
unreachable("Unknown hardware generation");
}
.addr = {
.buffer = buffer->bo,
.offset = buffer->offset + offset,
+ .mocs = device->default_mocs,
},
};
assert(ok);
}
+#define ANV_AUX_USAGE_DEFAULT ((enum isl_aux_usage)0xff)
+
+static struct blorp_address
+anv_to_blorp_address(struct anv_address addr)
+{
+ return (struct blorp_address) {
+ .buffer = addr.bo,
+ .offset = addr.offset,
+ };
+}
+
static void
-get_blorp_surf_for_anv_image(const struct anv_image *image,
+get_blorp_surf_for_anv_image(const struct anv_device *device,
+ const struct anv_image *image,
VkImageAspectFlags aspect,
enum isl_aux_usage aux_usage,
struct blorp_surf *blorp_surf)
{
+ uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
+
+ if (aux_usage == ANV_AUX_USAGE_DEFAULT)
+ aux_usage = image->planes[plane].aux_usage;
+
if (aspect == VK_IMAGE_ASPECT_STENCIL_BIT ||
aux_usage == ISL_AUX_USAGE_HIZ)
aux_usage = ISL_AUX_USAGE_NONE;
- const struct anv_surface *surface =
- anv_image_get_surface_for_aspect_mask(image, aspect);
-
+ const struct anv_surface *surface = &image->planes[plane].surface;
*blorp_surf = (struct blorp_surf) {
.surf = &surface->isl,
.addr = {
- .buffer = image->bo,
- .offset = image->offset + surface->offset,
+ .buffer = image->planes[plane].bo,
+ .offset = image->planes[plane].bo_offset + surface->offset,
+ .mocs = device->default_mocs,
},
};
if (aux_usage != ISL_AUX_USAGE_NONE) {
- blorp_surf->aux_surf = &image->aux_surface.isl,
+ const struct anv_surface *aux_surface = &image->planes[plane].aux_surface;
+ blorp_surf->aux_surf = &aux_surface->isl,
blorp_surf->aux_addr = (struct blorp_address) {
- .buffer = image->bo,
- .offset = image->offset + image->aux_surface.offset,
+ .buffer = image->planes[plane].bo,
+ .offset = image->planes[plane].bo_offset + aux_surface->offset,
+ .mocs = device->default_mocs,
};
blorp_surf->aux_usage = aux_usage;
}
anv_get_layerCount(src_image, &pRegions[r].srcSubresource));
}
- assert(pRegions[r].srcSubresource.aspectMask ==
- pRegions[r].dstSubresource.aspectMask);
-
- uint32_t a;
- for_each_bit(a, pRegions[r].dstSubresource.aspectMask) {
- VkImageAspectFlagBits aspect = (1 << a);
-
+ VkImageAspectFlags src_mask = pRegions[r].srcSubresource.aspectMask,
+ dst_mask = pRegions[r].dstSubresource.aspectMask;
+
+ assert(anv_image_aspects_compatible(src_mask, dst_mask));
+
+ if (_mesa_bitcount(src_mask) > 1) {
+ uint32_t aspect_bit;
+ anv_foreach_image_aspect_bit(aspect_bit, src_image, src_mask) {
+ struct blorp_surf src_surf, dst_surf;
+ get_blorp_surf_for_anv_image(cmd_buffer->device,
+ src_image, 1UL << aspect_bit,
+ ANV_AUX_USAGE_DEFAULT, &src_surf);
+ get_blorp_surf_for_anv_image(cmd_buffer->device,
+ dst_image, 1UL << aspect_bit,
+ ANV_AUX_USAGE_DEFAULT, &dst_surf);
+
+ for (unsigned i = 0; i < layer_count; i++) {
+ blorp_copy(&batch, &src_surf, pRegions[r].srcSubresource.mipLevel,
+ src_base_layer + i,
+ &dst_surf, pRegions[r].dstSubresource.mipLevel,
+ dst_base_layer + i,
+ srcOffset.x, srcOffset.y,
+ dstOffset.x, dstOffset.y,
+ extent.width, extent.height);
+ }
+ }
+ } else {
struct blorp_surf src_surf, dst_surf;
- get_blorp_surf_for_anv_image(src_image, aspect, src_image->aux_usage,
- &src_surf);
- get_blorp_surf_for_anv_image(dst_image, aspect, dst_image->aux_usage,
- &dst_surf);
+ get_blorp_surf_for_anv_image(cmd_buffer->device, src_image, src_mask,
+ ANV_AUX_USAGE_DEFAULT, &src_surf);
+ get_blorp_surf_for_anv_image(cmd_buffer->device, dst_image, dst_mask,
+ ANV_AUX_USAGE_DEFAULT, &dst_surf);
for (unsigned i = 0; i < layer_count; i++) {
blorp_copy(&batch, &src_surf, pRegions[r].srcSubresource.mipLevel,
for (unsigned r = 0; r < regionCount; r++) {
const VkImageAspectFlags aspect = pRegions[r].imageSubresource.aspectMask;
- get_blorp_surf_for_anv_image(anv_image, aspect, anv_image->aux_usage,
- &image.surf);
+ get_blorp_surf_for_anv_image(cmd_buffer->device, anv_image, aspect,
+ ANV_AUX_USAGE_DEFAULT, &image.surf);
image.offset =
anv_sanitize_image_offset(anv_image->type, pRegions[r].imageOffset);
image.level = pRegions[r].imageSubresource.mipLevel;
const VkImageSubresourceLayers *src_res = &pRegions[r].srcSubresource;
const VkImageSubresourceLayers *dst_res = &pRegions[r].dstSubresource;
- get_blorp_surf_for_anv_image(src_image, src_res->aspectMask,
- src_image->aux_usage, &src);
- get_blorp_surf_for_anv_image(dst_image, dst_res->aspectMask,
- dst_image->aux_usage, &dst);
+ get_blorp_surf_for_anv_image(cmd_buffer->device,
+ src_image, src_res->aspectMask,
+ ANV_AUX_USAGE_DEFAULT, &src);
+ get_blorp_surf_for_anv_image(cmd_buffer->device,
+ dst_image, dst_res->aspectMask,
+ ANV_AUX_USAGE_DEFAULT, &dst);
- struct anv_format src_format =
- anv_get_format(&cmd_buffer->device->info, src_image->vk_format,
- src_res->aspectMask, src_image->tiling);
- struct anv_format dst_format =
- anv_get_format(&cmd_buffer->device->info, dst_image->vk_format,
- dst_res->aspectMask, dst_image->tiling);
+ struct anv_format_plane src_format =
+ anv_get_format_plane(&cmd_buffer->device->info, src_image->vk_format,
+ src_res->aspectMask, src_image->tiling);
+ struct anv_format_plane dst_format =
+ anv_get_format_plane(&cmd_buffer->device->info, dst_image->vk_format,
+ dst_res->aspectMask, dst_image->tiling);
unsigned dst_start, dst_end;
if (dst_image->type == VK_IMAGE_TYPE_3D) {
isl_format_for_size(unsigned size_B)
{
switch (size_B) {
- case 1: return ISL_FORMAT_R8_UINT;
- case 2: return ISL_FORMAT_R8G8_UINT;
- case 4: return ISL_FORMAT_R8G8B8A8_UINT;
- case 8: return ISL_FORMAT_R16G16B16A16_UINT;
+ case 4: return ISL_FORMAT_R32_UINT;
+ case 8: return ISL_FORMAT_R32G32_UINT;
case 16: return ISL_FORMAT_R32G32B32A32_UINT;
default:
unreachable("Not a power-of-two format size");
}
}
-static void
-do_buffer_copy(struct blorp_batch *batch,
- struct anv_bo *src, uint64_t src_offset,
- struct anv_bo *dst, uint64_t dst_offset,
- int width, int height, int block_size)
-{
- struct anv_device *device = batch->blorp->driver_ctx;
-
- /* The actual format we pick doesn't matter as blorp will throw it away.
- * The only thing that actually matters is the size.
- */
- enum isl_format format = isl_format_for_size(block_size);
-
- struct isl_surf surf;
- isl_surf_init(&device->isl_dev, &surf,
- .dim = ISL_SURF_DIM_2D,
- .format = format,
- .width = width,
- .height = height,
- .depth = 1,
- .levels = 1,
- .array_len = 1,
- .samples = 1,
- .usage = ISL_SURF_USAGE_TEXTURE_BIT |
- ISL_SURF_USAGE_RENDER_TARGET_BIT,
- .tiling_flags = ISL_TILING_LINEAR_BIT);
- assert(surf.row_pitch == width * block_size);
-
- struct blorp_surf src_blorp_surf = {
- .surf = &surf,
- .addr = {
- .buffer = src,
- .offset = src_offset,
- },
- };
-
- struct blorp_surf dst_blorp_surf = {
- .surf = &surf,
- .addr = {
- .buffer = dst,
- .offset = dst_offset,
- },
- };
-
- blorp_copy(batch, &src_blorp_surf, 0, 0, &dst_blorp_surf, 0, 0,
- 0, 0, 0, 0, width, height);
-}
-
/**
* Returns the greatest common divisor of a and b that is a power of two.
*/
-static inline uint64_t
+static uint64_t
gcd_pow2_u64(uint64_t a, uint64_t b)
{
assert(a > 0 || b > 0);
blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
for (unsigned r = 0; r < regionCount; r++) {
- uint64_t src_offset = src_buffer->offset + pRegions[r].srcOffset;
- uint64_t dst_offset = dst_buffer->offset + pRegions[r].dstOffset;
- uint64_t copy_size = pRegions[r].size;
-
- /* First, we compute the biggest format that can be used with the
- * given offsets and size.
- */
- int bs = 16;
- bs = gcd_pow2_u64(bs, src_offset);
- bs = gcd_pow2_u64(bs, dst_offset);
- bs = gcd_pow2_u64(bs, pRegions[r].size);
-
- /* First, we make a bunch of max-sized copies */
- uint64_t max_copy_size = MAX_SURFACE_DIM * MAX_SURFACE_DIM * bs;
- while (copy_size >= max_copy_size) {
- do_buffer_copy(&batch, src_buffer->bo, src_offset,
- dst_buffer->bo, dst_offset,
- MAX_SURFACE_DIM, MAX_SURFACE_DIM, bs);
- copy_size -= max_copy_size;
- src_offset += max_copy_size;
- dst_offset += max_copy_size;
- }
-
- /* Now make a max-width copy */
- uint64_t height = copy_size / (MAX_SURFACE_DIM * bs);
- assert(height < MAX_SURFACE_DIM);
- if (height != 0) {
- uint64_t rect_copy_size = height * MAX_SURFACE_DIM * bs;
- do_buffer_copy(&batch, src_buffer->bo, src_offset,
- dst_buffer->bo, dst_offset,
- MAX_SURFACE_DIM, height, bs);
- copy_size -= rect_copy_size;
- src_offset += rect_copy_size;
- dst_offset += rect_copy_size;
- }
+ struct blorp_address src = {
+ .buffer = src_buffer->bo,
+ .offset = src_buffer->offset + pRegions[r].srcOffset,
+ .mocs = cmd_buffer->device->default_mocs,
+ };
+ struct blorp_address dst = {
+ .buffer = dst_buffer->bo,
+ .offset = dst_buffer->offset + pRegions[r].dstOffset,
+ .mocs = cmd_buffer->device->default_mocs,
+ };
- /* Finally, make a small copy to finish it off */
- if (copy_size != 0) {
- do_buffer_copy(&batch, src_buffer->bo, src_offset,
- dst_buffer->bo, dst_offset,
- copy_size / bs, 1, bs);
- }
+ blorp_buffer_copy(&batch, src, dst, pRegions[r].size);
}
blorp_batch_finish(&batch);
* little data at the top to build its linked list.
*/
const uint32_t max_update_size =
- cmd_buffer->device->dynamic_state_block_pool.block_size - 64;
+ cmd_buffer->device->dynamic_state_pool.block_size - 64;
assert(max_update_size < MAX_SURFACE_DIM * 4);
+ /* We're about to read data that was written from the CPU. Flush the
+ * texture cache so we don't get anything stale.
+ */
+ cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT;
+
while (dataSize) {
const uint32_t copy_size = MIN2(dataSize, max_update_size);
memcpy(tmp_data.map, pData, copy_size);
- int bs = 16;
- bs = gcd_pow2_u64(bs, dstOffset);
- bs = gcd_pow2_u64(bs, copy_size);
+ anv_state_flush(cmd_buffer->device, tmp_data);
- do_buffer_copy(&batch,
- &cmd_buffer->device->dynamic_state_block_pool.bo,
- tmp_data.offset,
- dst_buffer->bo, dst_buffer->offset + dstOffset,
- copy_size / bs, 1, bs);
+ struct blorp_address src = {
+ .buffer = &cmd_buffer->device->dynamic_state_pool.block_pool.bo,
+ .offset = tmp_data.offset,
+ .mocs = cmd_buffer->device->default_mocs,
+ };
+ struct blorp_address dst = {
+ .buffer = dst_buffer->bo,
+ .offset = dst_buffer->offset + dstOffset,
+ .mocs = cmd_buffer->device->default_mocs,
+ };
+
+ blorp_buffer_copy(&batch, src, dst, copy_size);
dataSize -= copy_size;
dstOffset += copy_size;
struct blorp_batch batch;
blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
- struct blorp_surf surf;
- get_blorp_surf_for_anv_image(image, VK_IMAGE_ASPECT_COLOR_BIT,
- image->aux_usage, &surf);
for (unsigned r = 0; r < rangeCount; r++) {
if (pRanges[r].aspectMask == 0)
continue;
- assert(pRanges[r].aspectMask == VK_IMAGE_ASPECT_COLOR_BIT);
+ assert(pRanges[r].aspectMask & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV);
- struct anv_format src_format =
- anv_get_format(&cmd_buffer->device->info, image->vk_format,
- VK_IMAGE_ASPECT_COLOR_BIT, image->tiling);
+ struct blorp_surf surf;
+ get_blorp_surf_for_anv_image(cmd_buffer->device,
+ image, pRanges[r].aspectMask,
+ ANV_AUX_USAGE_DEFAULT, &surf);
+
+ struct anv_format_plane src_format =
+ anv_get_format_plane(&cmd_buffer->device->info, image->vk_format,
+ VK_IMAGE_ASPECT_COLOR_BIT, image->tiling);
unsigned base_layer = pRanges[r].baseArrayLayer;
unsigned layer_count = anv_get_layerCount(image, &pRanges[r]);
struct blorp_surf depth, stencil;
if (image->aspects & VK_IMAGE_ASPECT_DEPTH_BIT) {
- get_blorp_surf_for_anv_image(image, VK_IMAGE_ASPECT_DEPTH_BIT,
+ get_blorp_surf_for_anv_image(cmd_buffer->device,
+ image, VK_IMAGE_ASPECT_DEPTH_BIT,
ISL_AUX_USAGE_NONE, &depth);
} else {
memset(&depth, 0, sizeof(depth));
}
if (image->aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
- get_blorp_surf_for_anv_image(image, VK_IMAGE_ASPECT_STENCIL_BIT,
+ get_blorp_surf_for_anv_image(cmd_buffer->device,
+ image, VK_IMAGE_ASPECT_STENCIL_BIT,
ISL_AUX_USAGE_NONE, &stencil);
} else {
memset(&stencil, 0, sizeof(stencil));
uint32_t binding_table;
VkResult result =
- binding_table_for_surface_state(cmd_buffer, att_state->color_rt_state,
+ binding_table_for_surface_state(cmd_buffer, att_state->color.state,
&binding_table);
if (result != VK_SUCCESS)
return;
union isl_color_value clear_color =
vk_to_isl_color(attachment->clearValue.color);
+ /* If multiview is enabled we ignore baseArrayLayer and layerCount */
+ if (subpass->view_mask) {
+ uint32_t view_idx;
+ for_each_bit(view_idx, subpass->view_mask) {
+ for (uint32_t r = 0; r < rectCount; ++r) {
+ const VkOffset2D offset = pRects[r].rect.offset;
+ const VkExtent2D extent = pRects[r].rect.extent;
+ blorp_clear_attachments(batch, binding_table,
+ ISL_FORMAT_UNSUPPORTED, pass_att->samples,
+ view_idx, 1,
+ offset.x, offset.y,
+ offset.x + extent.width,
+ offset.y + extent.height,
+ true, clear_color, false, 0.0f, 0, 0);
+ }
+ }
+ return;
+ }
+
for (uint32_t r = 0; r < rectCount; ++r) {
const VkOffset2D offset = pRects[r].rect.offset;
const VkExtent2D extent = pRects[r].rect.extent;
+ assert(pRects[r].layerCount != VK_REMAINING_ARRAY_LAYERS);
blorp_clear_attachments(batch, binding_table,
ISL_FORMAT_UNSUPPORTED, pass_att->samples,
pRects[r].baseArrayLayer,
if (result != VK_SUCCESS)
return;
+ /* If multiview is enabled we ignore baseArrayLayer and layerCount */
+ if (subpass->view_mask) {
+ uint32_t view_idx;
+ for_each_bit(view_idx, subpass->view_mask) {
+ for (uint32_t r = 0; r < rectCount; ++r) {
+ const VkOffset2D offset = pRects[r].rect.offset;
+ const VkExtent2D extent = pRects[r].rect.extent;
+ VkClearDepthStencilValue value = attachment->clearValue.depthStencil;
+ blorp_clear_attachments(batch, binding_table,
+ depth_format, pass_att->samples,
+ view_idx, 1,
+ offset.x, offset.y,
+ offset.x + extent.width,
+ offset.y + extent.height,
+ false, color_value,
+ clear_depth, value.depth,
+ clear_stencil ? 0xff : 0, value.stencil);
+ }
+ }
+ return;
+ }
+
for (uint32_t r = 0; r < rectCount; ++r) {
const VkOffset2D offset = pRects[r].rect.offset;
const VkExtent2D extent = pRects[r].rect.extent;
VkClearDepthStencilValue value = attachment->clearValue.depthStencil;
+ assert(pRects[r].layerCount != VK_REMAINING_ARRAY_LAYERS);
blorp_clear_attachments(batch, binding_table,
depth_format, pass_att->samples,
pRects[r].baseArrayLayer,
BLORP_BATCH_NO_EMIT_DEPTH_STENCIL);
for (uint32_t a = 0; a < attachmentCount; ++a) {
- if (pAttachments[a].aspectMask == VK_IMAGE_ASPECT_COLOR_BIT) {
+ if (pAttachments[a].aspectMask & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) {
+ assert(pAttachments[a].aspectMask == VK_IMAGE_ASPECT_COLOR_BIT);
clear_color_attachment(cmd_buffer, &batch,
&pAttachments[a],
rectCount, pRects);
for (uint32_t i = 0; i < cmd_state->subpass->color_count; ++i) {
uint32_t a = cmd_state->subpass->color_attachments[i].attachment;
+ if (a == VK_ATTACHMENT_UNUSED)
+ continue;
+
+ assert(a < cmd_state->pass->attachment_count);
if (cmd_state->attachments[a].pending_clear_aspects) {
return true;
}
}
- if (ds != VK_ATTACHMENT_UNUSED &&
- cmd_state->attachments[ds].pending_clear_aspects) {
- return true;
+ if (ds != VK_ATTACHMENT_UNUSED) {
+ assert(ds < cmd_state->pass->attachment_count);
+ if (cmd_state->attachments[ds].pending_clear_aspects)
+ return true;
}
return false;
struct anv_framebuffer *fb = cmd_buffer->state.framebuffer;
for (uint32_t i = 0; i < cmd_state->subpass->color_count; ++i) {
const uint32_t a = cmd_state->subpass->color_attachments[i].attachment;
+ if (a == VK_ATTACHMENT_UNUSED)
+ continue;
+
+ assert(a < cmd_state->pass->attachment_count);
struct anv_attachment_state *att_state = &cmd_state->attachments[a];
if (!att_state->pending_clear_aspects)
struct anv_image_view *iview = fb->attachments[a];
const struct anv_image *image = iview->image;
struct blorp_surf surf;
- get_blorp_surf_for_anv_image(image, VK_IMAGE_ASPECT_COLOR_BIT,
+ get_blorp_surf_for_anv_image(cmd_buffer->device,
+ image, VK_IMAGE_ASPECT_COLOR_BIT,
att_state->aux_usage, &surf);
if (att_state->fast_clear) {
cmd_buffer->state.pending_pipe_bits |=
ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_CS_STALL_BIT;
- blorp_fast_clear(&batch, &surf, iview->isl.format,
- iview->isl.base_level,
- iview->isl.base_array_layer, fb->layers,
+ assert(image->n_planes == 1);
+ blorp_fast_clear(&batch, &surf, iview->planes[0].isl.format,
+ iview->planes[0].isl.base_level,
+ iview->planes[0].isl.base_array_layer, fb->layers,
render_area.offset.x, render_area.offset.y,
render_area.offset.x + render_area.extent.width,
render_area.offset.y + render_area.extent.height);
cmd_buffer->state.pending_pipe_bits |=
ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_CS_STALL_BIT;
} else {
- blorp_clear(&batch, &surf, iview->isl.format,
- anv_swizzle_for_render(iview->isl.swizzle),
- iview->isl.base_level,
- iview->isl.base_array_layer, fb->layers,
+ assert(image->n_planes == 1);
+ blorp_clear(&batch, &surf, iview->planes[0].isl.format,
+ anv_swizzle_for_render(iview->planes[0].isl.swizzle),
+ iview->planes[0].isl.base_level,
+ iview->planes[0].isl.base_array_layer, fb->layers,
render_area.offset.x, render_area.offset.y,
render_area.offset.x + render_area.extent.width,
render_area.offset.y + render_area.extent.height,
}
const uint32_t ds = cmd_state->subpass->depth_stencil_attachment.attachment;
+ assert(ds == VK_ATTACHMENT_UNUSED || ds < cmd_state->pass->attachment_count);
if (ds != VK_ATTACHMENT_UNUSED &&
cmd_state->attachments[ds].pending_clear_aspects) {
* a stencil clear in addition to using the BLORP-fallback for depth.
*/
if (clear_depth) {
- if (!blorp_can_hiz_clear_depth(gen, iview->isl.format,
+ if (!blorp_can_hiz_clear_depth(gen, iview->planes[0].isl.format,
iview->image->samples,
render_area.offset.x,
render_area.offset.y,
clear_with_hiz = false;
} else if (gen == 8 &&
anv_can_sample_with_hiz(&cmd_buffer->device->info,
- iview->aspect_mask,
- iview->image->samples)) {
+ iview->image)) {
/* Only gen9+ supports returning ANV_HZ_FC_VAL when sampling a
* fast-cleared portion of a HiZ buffer. Testing has revealed
* that Gen8 only supports returning 0.0f. Gens prior to gen8 do
clear_depth, clear_stencil,
clear_att.clearValue.
depthStencil.stencil);
+
+ /* From the SKL PRM, Depth Buffer Clear:
+ *
+ * Depth Buffer Clear Workaround
+ * Depth buffer clear pass using any of the methods (WM_STATE,
+ * 3DSTATE_WM or 3DSTATE_WM_HZ_OP) must be followed by a
+ * PIPE_CONTROL command with DEPTH_STALL bit and Depth FLUSH bits
+ * “set” before starting to render. DepthStall and DepthFlush are
+ * not needed between consecutive depth clear passes nor is it
+ * required if the depth-clear pass was done with “full_surf_clear”
+ * bit set in the 3DSTATE_WM_HZ_OP.
+ */
+ if (clear_depth) {
+ cmd_buffer->state.pending_pipe_bits |=
+ ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | ANV_PIPE_DEPTH_STALL_BIT;
+ }
}
}
}
static void
-resolve_image(struct blorp_batch *batch,
+resolve_surface(struct blorp_batch *batch,
+ struct blorp_surf *src_surf,
+ uint32_t src_level, uint32_t src_layer,
+ struct blorp_surf *dst_surf,
+ uint32_t dst_level, uint32_t dst_layer,
+ uint32_t src_x, uint32_t src_y, uint32_t dst_x, uint32_t dst_y,
+ uint32_t width, uint32_t height)
+{
+ blorp_blit(batch,
+ src_surf, src_level, src_layer,
+ ISL_FORMAT_UNSUPPORTED, ISL_SWIZZLE_IDENTITY,
+ dst_surf, dst_level, dst_layer,
+ ISL_FORMAT_UNSUPPORTED, ISL_SWIZZLE_IDENTITY,
+ src_x, src_y, src_x + width, src_y + height,
+ dst_x, dst_y, dst_x + width, dst_y + height,
+ 0x2600 /* GL_NEAREST */, false, false);
+}
+
+static void
+resolve_image(struct anv_device *device,
+ struct blorp_batch *batch,
const struct anv_image *src_image,
uint32_t src_level, uint32_t src_layer,
const struct anv_image *dst_image,
assert(src_image->samples > 1);
assert(dst_image->type == VK_IMAGE_TYPE_2D);
assert(dst_image->samples == 1);
+ assert(src_image->n_planes == dst_image->n_planes);
- uint32_t a;
- for_each_bit(a, aspect_mask) {
- VkImageAspectFlagBits aspect = 1 << a;
+ uint32_t aspect_bit;
+ anv_foreach_image_aspect_bit(aspect_bit, src_image, aspect_mask) {
struct blorp_surf src_surf, dst_surf;
- get_blorp_surf_for_anv_image(src_image, aspect,
- src_image->aux_usage, &src_surf);
- get_blorp_surf_for_anv_image(dst_image, aspect,
- dst_image->aux_usage, &dst_surf);
-
- blorp_blit(batch,
- &src_surf, src_level, src_layer,
- ISL_FORMAT_UNSUPPORTED, ISL_SWIZZLE_IDENTITY,
- &dst_surf, dst_level, dst_layer,
- ISL_FORMAT_UNSUPPORTED, ISL_SWIZZLE_IDENTITY,
- src_x, src_y, src_x + width, src_y + height,
- dst_x, dst_y, dst_x + width, dst_y + height,
- 0x2600 /* GL_NEAREST */, false, false);
+ get_blorp_surf_for_anv_image(device, src_image, 1UL << aspect_bit,
+ ANV_AUX_USAGE_DEFAULT, &src_surf);
+ get_blorp_surf_for_anv_image(device, dst_image, 1UL << aspect_bit,
+ ANV_AUX_USAGE_DEFAULT, &dst_surf);
+
+ assert(!src_image->format->can_ycbcr);
+ assert(!dst_image->format->can_ycbcr);
+
+ resolve_surface(batch,
+ &src_surf, src_level, src_layer,
+ &dst_surf, dst_level, dst_layer,
+ src_x, src_y, dst_x, dst_y, width, height);
}
}
const uint32_t layer_count =
anv_get_layerCount(dst_image, &pRegions[r].dstSubresource);
+ VkImageAspectFlags src_mask = pRegions[r].srcSubresource.aspectMask,
+ dst_mask = pRegions[r].dstSubresource.aspectMask;
+
+ assert(anv_image_aspects_compatible(src_mask, dst_mask));
+
for (uint32_t layer = 0; layer < layer_count; layer++) {
- resolve_image(&batch,
- src_image, pRegions[r].srcSubresource.mipLevel,
+ resolve_image(cmd_buffer->device, &batch,
+ src_image,
+ pRegions[r].srcSubresource.mipLevel,
pRegions[r].srcSubresource.baseArrayLayer + layer,
- dst_image, pRegions[r].dstSubresource.mipLevel,
+ dst_image,
+ pRegions[r].dstSubresource.mipLevel,
pRegions[r].dstSubresource.baseArrayLayer + layer,
pRegions[r].dstSubresource.aspectMask,
pRegions[r].srcOffset.x, pRegions[r].srcOffset.y,
blorp_batch_finish(&batch);
}
-static void
-ccs_resolve_attachment(struct anv_cmd_buffer *cmd_buffer,
- struct blorp_batch *batch,
- uint32_t att)
+static enum isl_aux_usage
+fast_clear_aux_usage(const struct anv_image *image,
+ VkImageAspectFlagBits aspect)
{
- struct anv_framebuffer *fb = cmd_buffer->state.framebuffer;
- struct anv_attachment_state *att_state =
- &cmd_buffer->state.attachments[att];
-
- if (att_state->aux_usage == ISL_AUX_USAGE_NONE ||
- att_state->aux_usage == ISL_AUX_USAGE_MCS)
- return; /* Nothing to resolve */
-
- assert(att_state->aux_usage == ISL_AUX_USAGE_CCS_E ||
- att_state->aux_usage == ISL_AUX_USAGE_CCS_D);
-
- struct anv_render_pass *pass = cmd_buffer->state.pass;
- const uint32_t subpass_idx = anv_get_subpass_id(&cmd_buffer->state);
+ uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
+ if (image->planes[plane].aux_usage == ISL_AUX_USAGE_NONE)
+ return ISL_AUX_USAGE_CCS_D;
+ else
+ return image->planes[plane].aux_usage;
+}
- /* Scan forward to see what all ways this attachment will be used.
- * Ideally, we would like to resolve in the same subpass as the last write
- * of a particular attachment. That way we only resolve once but it's
- * still hot in the cache.
- */
- bool found_draw = false;
- bool self_dep = false;
- enum anv_subpass_usage usage = 0;
- for (uint32_t s = subpass_idx + 1; s < pass->subpass_count; s++) {
- usage |= pass->attachments[att].subpass_usage[s];
-
- if (usage & (ANV_SUBPASS_USAGE_DRAW | ANV_SUBPASS_USAGE_RESOLVE_DST)) {
- /* We found another subpass that draws to this attachment. We'll
- * wait to resolve until then.
- */
- found_draw = true;
- if (pass->attachments[att].subpass_usage[s] & ANV_SUBPASS_USAGE_INPUT)
- self_dep = true;
- break;
- }
- }
+void
+anv_image_fast_clear(struct anv_cmd_buffer *cmd_buffer,
+ const struct anv_image *image,
+ VkImageAspectFlagBits aspect,
+ const uint32_t base_level, const uint32_t level_count,
+ const uint32_t base_layer, uint32_t layer_count)
+{
+ assert(image->type == VK_IMAGE_TYPE_3D || image->extent.depth == 1);
- struct anv_image_view *iview = fb->attachments[att];
- const struct anv_image *image = iview->image;
- assert(image->aspects == VK_IMAGE_ASPECT_COLOR_BIT);
-
- enum blorp_fast_clear_op resolve_op = BLORP_FAST_CLEAR_OP_NONE;
- if (!found_draw) {
- /* This is the last subpass that writes to this attachment so we need to
- * resolve here. Ideally, we would like to only resolve if the storeOp
- * is set to VK_ATTACHMENT_STORE_OP_STORE. However, we need to ensure
- * that the CCS bits are set to "resolved" because there may be copy or
- * blit operations (which may ignore CCS) between now and the next time
- * we render and we need to ensure that anything they write will be
- * respected in the next render. Unfortunately, the hardware does not
- * provide us with any sort of "invalidate" pass that sets the CCS to
- * "resolved" without writing to the render target.
- */
- if (iview->image->aux_usage != ISL_AUX_USAGE_CCS_E) {
- /* The image destination surface doesn't support compression outside
- * the render pass. We need a full resolve.
- */
- resolve_op = BLORP_FAST_CLEAR_OP_RESOLVE_FULL;
- } else if (att_state->fast_clear) {
- /* We don't know what to do with clear colors outside the render
- * pass. We need a partial resolve. Only transparent black is
- * built into the surface state object and thus no resolve is
- * required for this case.
- */
- if (att_state->clear_value.color.uint32[0] ||
- att_state->clear_value.color.uint32[1] ||
- att_state->clear_value.color.uint32[2] ||
- att_state->clear_value.color.uint32[3])
- resolve_op = BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL;
- } else {
- /* The image "natively" supports all the compression we care about
- * and we don't need to resolve at all. If this is the case, we also
- * don't need to resolve for any of the input attachment cases below.
- */
- }
- } else if (usage & ANV_SUBPASS_USAGE_INPUT) {
- /* Input attachments are clear-color aware so, at least on Sky Lake, we
- * can frequently sample from them with no resolves at all.
- */
- if (att_state->aux_usage != att_state->input_aux_usage) {
- assert(att_state->input_aux_usage == ISL_AUX_USAGE_NONE);
- resolve_op = BLORP_FAST_CLEAR_OP_RESOLVE_FULL;
- } else if (!att_state->clear_color_is_zero_one) {
- /* Sky Lake PRM, Vol. 2d, RENDER_SURFACE_STATE::Red Clear Color:
- *
- * "If Number of Multisamples is MULTISAMPLECOUNT_1 AND if this RT
- * is fast cleared with non-0/1 clear value, this RT must be
- * partially resolved (refer to Partial Resolve operation) before
- * binding this surface to Sampler."
- */
- resolve_op = BLORP_FAST_CLEAR_OP_RESOLVE_PARTIAL;
- } else if (cmd_buffer->device->info.gen == 8 && self_dep &&
- att_state->input_aux_usage == ISL_AUX_USAGE_CCS_D) {
- /* On Broadwell we still need to do resolves when there is a
- * self-dependency because HW could not see fast-clears and works
- * on the render cache as if there was regular non-fast-clear surface.
- * To avoid any inconsistency, we force the resolve.
- */
- resolve_op = BLORP_FAST_CLEAR_OP_RESOLVE_FULL;
- }
+ if (image->type == VK_IMAGE_TYPE_3D) {
+ assert(base_layer == 0);
+ assert(layer_count == anv_minify(image->extent.depth, base_level));
}
- if (resolve_op == BLORP_FAST_CLEAR_OP_NONE)
- return;
+ struct blorp_batch batch;
+ blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
struct blorp_surf surf;
- get_blorp_surf_for_anv_image(image, VK_IMAGE_ASPECT_COLOR_BIT,
- att_state->aux_usage, &surf);
- if (att_state->fast_clear)
- surf.clear_color = vk_to_isl_color(att_state->clear_value.color);
+ get_blorp_surf_for_anv_image(cmd_buffer->device, image, aspect,
+ fast_clear_aux_usage(image, aspect),
+ &surf);
- /* From the Sky Lake PRM Vol. 7, "Render Target Resolve":
+ /* From the Sky Lake PRM Vol. 7, "Render Target Fast Clear":
*
- * "When performing a render target resolve, PIPE_CONTROL with end of
- * pipe sync must be delivered."
+ * "After Render target fast clear, pipe-control with color cache
+ * write-flush must be issued before sending any DRAW commands on
+ * that render target."
*
* This comment is a bit cryptic and doesn't really tell you what's going
* or what's really needed. It appears that fast clear ops are not
- * properly synchronized with other drawing. We need to use a PIPE_CONTROL
- * to ensure that the contents of the previous draw hit the render target
- * before we resolve and then use a second PIPE_CONTROL after the resolve
- * to ensure that it is completed before any additional drawing occurs.
+ * properly synchronized with other drawing. This means that we cannot
+ * have a fast clear operation in the pipe at the same time as other
+ * regular drawing operations. We need to use a PIPE_CONTROL to ensure
+ * that the contents of the previous draw hit the render target before we
+ * resolve and then use a second PIPE_CONTROL after the resolve to ensure
+ * that it is completed before any additional drawing occurs.
*/
cmd_buffer->state.pending_pipe_bits |=
ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_CS_STALL_BIT;
- for (uint32_t layer = 0; layer < fb->layers; layer++) {
- blorp_ccs_resolve(batch, &surf,
- iview->isl.base_level,
- iview->isl.base_array_layer + layer,
- iview->isl.format, resolve_op);
+ uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
+ uint32_t width_div = image->format->planes[plane].denominator_scales[0];
+ uint32_t height_div = image->format->planes[plane].denominator_scales[1];
+
+ for (uint32_t l = 0; l < level_count; l++) {
+ const uint32_t level = base_level + l;
+
+ const VkExtent3D extent = {
+ .width = anv_minify(image->extent.width, level),
+ .height = anv_minify(image->extent.height, level),
+ .depth = anv_minify(image->extent.depth, level),
+ };
+
+ if (image->type == VK_IMAGE_TYPE_3D)
+ layer_count = extent.depth;
+
+ assert(level < anv_image_aux_levels(image, aspect));
+ assert(base_layer + layer_count <= anv_image_aux_layers(image, aspect, level));
+ blorp_fast_clear(&batch, &surf, surf.surf->format,
+ level, base_layer, layer_count,
+ 0, 0,
+ extent.width / width_div,
+ extent.height / height_div);
}
cmd_buffer->state.pending_pipe_bits |=
ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_CS_STALL_BIT;
-
- /* Once we've done any sort of resolve, we're no longer fast-cleared */
- att_state->fast_clear = false;
- if (att_state->aux_usage == ISL_AUX_USAGE_CCS_D)
- att_state->aux_usage = ISL_AUX_USAGE_NONE;
}
void
struct anv_framebuffer *fb = cmd_buffer->state.framebuffer;
struct anv_subpass *subpass = cmd_buffer->state.subpass;
-
- struct blorp_batch batch;
- blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
-
- for (uint32_t i = 0; i < subpass->color_count; ++i) {
- ccs_resolve_attachment(cmd_buffer, &batch,
- subpass->color_attachments[i].attachment);
- }
-
if (subpass->has_resolve) {
+ struct blorp_batch batch;
+ blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
+
/* We are about to do some MSAA resolves. We need to flush so that the
* result of writes to the MSAA color attachments show up in the sampler
* when we blit to the single-sampled resolve target.
if (dst_att == VK_ATTACHMENT_UNUSED)
continue;
+ assert(src_att < cmd_buffer->state.pass->attachment_count);
+ assert(dst_att < cmd_buffer->state.pass->attachment_count);
+
if (cmd_buffer->state.attachments[dst_att].pending_clear_aspects) {
/* From the Vulkan 1.0 spec:
*
struct anv_image_view *src_iview = fb->attachments[src_att];
struct anv_image_view *dst_iview = fb->attachments[dst_att];
+ enum isl_aux_usage src_aux_usage =
+ cmd_buffer->state.attachments[src_att].aux_usage;
+ enum isl_aux_usage dst_aux_usage =
+ cmd_buffer->state.attachments[dst_att].aux_usage;
+
const VkRect2D render_area = cmd_buffer->state.render_area;
- assert(src_iview->aspect_mask == dst_iview->aspect_mask);
- resolve_image(&batch, src_iview->image,
- src_iview->isl.base_level,
- src_iview->isl.base_array_layer,
- dst_iview->image,
- dst_iview->isl.base_level,
- dst_iview->isl.base_array_layer,
- src_iview->aspect_mask,
- render_area.offset.x, render_area.offset.y,
- render_area.offset.x, render_area.offset.y,
- render_area.extent.width, render_area.extent.height);
-
- ccs_resolve_attachment(cmd_buffer, &batch, dst_att);
+ assert(src_iview->aspect_mask == VK_IMAGE_ASPECT_COLOR_BIT &&
+ dst_iview->aspect_mask == VK_IMAGE_ASPECT_COLOR_BIT);
+
+ struct blorp_surf src_surf, dst_surf;
+ get_blorp_surf_for_anv_image(cmd_buffer->device, src_iview->image,
+ VK_IMAGE_ASPECT_COLOR_BIT,
+ src_aux_usage, &src_surf);
+ get_blorp_surf_for_anv_image(cmd_buffer->device, dst_iview->image,
+ VK_IMAGE_ASPECT_COLOR_BIT,
+ dst_aux_usage, &dst_surf);
+
+ assert(!src_iview->image->format->can_ycbcr);
+ assert(!dst_iview->image->format->can_ycbcr);
+
+ resolve_surface(&batch,
+ &src_surf,
+ src_iview->planes[0].isl.base_level,
+ src_iview->planes[0].isl.base_array_layer,
+ &dst_surf,
+ dst_iview->planes[0].isl.base_level,
+ dst_iview->planes[0].isl.base_array_layer,
+ render_area.offset.x, render_area.offset.y,
+ render_area.offset.x, render_area.offset.y,
+ render_area.extent.width, render_area.extent.height);
+ }
+
+ blorp_batch_finish(&batch);
+ }
+}
+
+void
+anv_image_copy_to_shadow(struct anv_cmd_buffer *cmd_buffer,
+ const struct anv_image *image,
+ uint32_t base_level, uint32_t level_count,
+ uint32_t base_layer, uint32_t layer_count)
+{
+ struct blorp_batch batch;
+ blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
+
+ assert(image->aspects == VK_IMAGE_ASPECT_COLOR_BIT && image->n_planes == 1);
+
+ struct blorp_surf surf;
+ get_blorp_surf_for_anv_image(cmd_buffer->device,
+ image, VK_IMAGE_ASPECT_COLOR_BIT,
+ ISL_AUX_USAGE_NONE, &surf);
+
+ struct blorp_surf shadow_surf = {
+ .surf = &image->planes[0].shadow_surface.isl,
+ .addr = {
+ .buffer = image->planes[0].bo,
+ .offset = image->planes[0].bo_offset +
+ image->planes[0].shadow_surface.offset,
+ .mocs = cmd_buffer->device->default_mocs,
+ },
+ };
+
+ for (uint32_t l = 0; l < level_count; l++) {
+ const uint32_t level = base_level + l;
+
+ const VkExtent3D extent = {
+ .width = anv_minify(image->extent.width, level),
+ .height = anv_minify(image->extent.height, level),
+ .depth = anv_minify(image->extent.depth, level),
+ };
+
+ if (image->type == VK_IMAGE_TYPE_3D)
+ layer_count = extent.depth;
+
+ for (uint32_t a = 0; a < layer_count; a++) {
+ const uint32_t layer = base_layer + a;
+
+ blorp_copy(&batch, &surf, level, layer,
+ &shadow_surf, level, layer,
+ 0, 0, 0, 0, extent.width, extent.height);
}
}
{
assert(image);
+ assert(anv_image_aspect_to_plane(image->aspects,
+ VK_IMAGE_ASPECT_DEPTH_BIT) == 0);
+
/* Don't resolve depth buffers without an auxiliary HiZ buffer and
* don't perform such a resolve on gens that don't support it.
*/
if (cmd_buffer->device->info.gen < 8 ||
- image->aux_usage != ISL_AUX_USAGE_HIZ)
+ image->planes[0].aux_usage != ISL_AUX_USAGE_HIZ)
return;
assert(op == BLORP_HIZ_OP_HIZ_RESOLVE ||
blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
struct blorp_surf surf;
- get_blorp_surf_for_anv_image(image, VK_IMAGE_ASPECT_DEPTH_BIT,
+ get_blorp_surf_for_anv_image(cmd_buffer->device,
+ image, VK_IMAGE_ASPECT_DEPTH_BIT,
ISL_AUX_USAGE_NONE, &surf);
/* Manually add the aux HiZ surf */
- surf.aux_surf = &image->aux_surface.isl,
+ surf.aux_surf = &image->planes[0].aux_surface.isl,
surf.aux_addr = (struct blorp_address) {
- .buffer = image->bo,
- .offset = image->offset + image->aux_surface.offset,
+ .buffer = image->planes[0].bo,
+ .offset = image->planes[0].bo_offset +
+ image->planes[0].aux_surface.offset,
+ .mocs = cmd_buffer->device->default_mocs,
};
surf.aux_usage = ISL_AUX_USAGE_HIZ;
- surf.clear_color.u32[0] = (uint32_t) ANV_HZ_FC_VAL;
+ surf.clear_color.f32[0] = ANV_HZ_FC_VAL;
+
+ blorp_hiz_op(&batch, &surf, 0, 0, 1, op);
+ blorp_batch_finish(&batch);
+}
+
+void
+anv_ccs_resolve(struct anv_cmd_buffer * const cmd_buffer,
+ const struct anv_image * const image,
+ VkImageAspectFlagBits aspect,
+ const uint8_t level,
+ const uint32_t start_layer, const uint32_t layer_count,
+ const enum blorp_fast_clear_op op)
+{
+ assert(cmd_buffer && image);
+
+ uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
+
+ /* The resolved subresource range must have a CCS buffer. */
+ assert(level < anv_image_aux_levels(image, aspect));
+ assert(start_layer + layer_count <=
+ anv_image_aux_layers(image, aspect, level));
+ assert(image->aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV && image->samples == 1);
+
+ struct blorp_batch batch;
+ blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer,
+ BLORP_BATCH_PREDICATE_ENABLE);
+
+ struct blorp_surf surf;
+ get_blorp_surf_for_anv_image(cmd_buffer->device, image, aspect,
+ fast_clear_aux_usage(image, aspect),
+ &surf);
+ surf.clear_color_addr = anv_to_blorp_address(
+ anv_image_get_clear_color_addr(cmd_buffer->device, image, aspect, level));
+
+ blorp_ccs_resolve(&batch, &surf, level, start_layer, layer_count,
+ image->planes[plane].surface.isl.format, op);
- blorp_gen6_hiz_op(&batch, &surf, 0, 0, op);
blorp_batch_finish(&batch);
}
projects / mesa.git / blobdiff