}
static bool
-upload_blorp_shader(struct blorp_batch *batch,
+upload_blorp_shader(struct blorp_batch *batch, uint32_t stage,
const void *key, uint32_t key_size,
const void *kernel, uint32_t kernel_size,
const struct brw_stage_prog_data *prog_data,
};
struct anv_shader_bin *bin =
- anv_pipeline_cache_upload_kernel(&device->default_pipeline_cache,
+ anv_pipeline_cache_upload_kernel(&device->default_pipeline_cache, stage,
key, key_size, kernel, kernel_size,
- NULL, 0,
prog_data, prog_data_size,
NULL, 0, NULL, &bind_map);
bool dst_has_shadow = false;
struct blorp_surf dst_shadow_surf;
if (&image == dst) {
+ /* In this case, the source is the buffer and, since blorp takes its
+ * copy dimensions in terms of the source format, we have to use the
+ * scaled down version for compressed textures because the source
+ * format is an RGB format.
+ */
+ extent.width = buffer_extent.width;
+ extent.height = buffer_extent.height;
+
anv_cmd_buffer_mark_image_written(cmd_buffer, anv_image,
aspect, dst->surf.aux_usage,
dst->level,
* cache before rendering to it.
*/
cmd_buffer->state.pending_pipe_bits |=
- ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | ANV_PIPE_CS_STALL_BIT;
+ ANV_PIPE_DEPTH_CACHE_FLUSH_BIT | ANV_PIPE_END_OF_PIPE_SYNC_BIT;
blorp_clear_depth_stencil(&batch, &depth, &stencil,
level, base_layer, layer_count,
* cache before someone starts trying to do stencil on it.
*/
cmd_buffer->state.pending_pipe_bits |=
- ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_CS_STALL_BIT;
+ ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_END_OF_PIPE_SYNC_BIT;
struct blorp_surf stencil_shadow;
if ((aspects & VK_IMAGE_ASPECT_STENCIL_BIT) &&
{
assert(aspect == VK_IMAGE_ASPECT_DEPTH_BIT);
assert(base_layer + layer_count <= anv_image_aux_layers(image, aspect, level));
- assert(anv_image_aspect_to_plane(image->aspects,
- VK_IMAGE_ASPECT_DEPTH_BIT) == 0);
+ uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
+ assert(plane == 0);
struct blorp_batch batch;
blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0);
get_blorp_surf_for_anv_image(cmd_buffer->device,
image, VK_IMAGE_ASPECT_DEPTH_BIT,
0, ANV_IMAGE_LAYOUT_EXPLICIT_AUX,
- ISL_AUX_USAGE_HIZ, &surf);
+ image->planes[plane].aux_usage, &surf);
surf.clear_color.f32[0] = ANV_HZ_FC_VAL;
blorp_hiz_op(&batch, &surf, level, base_layer, layer_count, hiz_op);
struct blorp_surf depth = {};
if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT) {
+ uint32_t plane = anv_image_aspect_to_plane(image->aspects,
+ VK_IMAGE_ASPECT_DEPTH_BIT);
assert(base_layer + layer_count <=
anv_image_aux_layers(image, VK_IMAGE_ASPECT_DEPTH_BIT, level));
get_blorp_surf_for_anv_image(cmd_buffer->device,
image, VK_IMAGE_ASPECT_DEPTH_BIT,
0, ANV_IMAGE_LAYOUT_EXPLICIT_AUX,
- ISL_AUX_USAGE_HIZ, &depth);
+ image->planes[plane].aux_usage, &depth);
depth.clear_color.f32[0] = ANV_HZ_FC_VAL;
}
struct blorp_surf stencil = {};
if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
+ uint32_t plane = anv_image_aspect_to_plane(image->aspects,
+ VK_IMAGE_ASPECT_STENCIL_BIT);
get_blorp_surf_for_anv_image(cmd_buffer->device,
image, VK_IMAGE_ASPECT_STENCIL_BIT,
0, ANV_IMAGE_LAYOUT_EXPLICIT_AUX,
- ISL_AUX_USAGE_NONE, &stencil);
+ image->planes[plane].aux_usage, &stencil);
}
/* From the Sky Lake PRM Volume 7, "Depth Buffer Clear":
void
anv_image_mcs_op(struct anv_cmd_buffer *cmd_buffer,
const struct anv_image *image,
- enum isl_format format,
+ enum isl_format format, struct isl_swizzle swizzle,
VkImageAspectFlagBits aspect,
uint32_t base_layer, uint32_t layer_count,
enum isl_aux_op mcs_op, union isl_color_value *clear_value,
* that it is completed before any additional drawing occurs.
*/
cmd_buffer->state.pending_pipe_bits |=
- ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_CS_STALL_BIT;
+ ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_END_OF_PIPE_SYNC_BIT;
switch (mcs_op) {
case ISL_AUX_OP_FAST_CLEAR:
- blorp_fast_clear(&batch, &surf, format,
+ blorp_fast_clear(&batch, &surf, format, swizzle,
0, base_layer, layer_count,
0, 0, image->extent.width, image->extent.height);
break;
}
cmd_buffer->state.pending_pipe_bits |=
- ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_CS_STALL_BIT;
+ ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_END_OF_PIPE_SYNC_BIT;
blorp_batch_finish(&batch);
}
void
anv_image_ccs_op(struct anv_cmd_buffer *cmd_buffer,
const struct anv_image *image,
- enum isl_format format,
+ enum isl_format format, struct isl_swizzle swizzle,
VkImageAspectFlagBits aspect, uint32_t level,
uint32_t base_layer, uint32_t layer_count,
enum isl_aux_op ccs_op, union isl_color_value *clear_value,
* that it is completed before any additional drawing occurs.
*/
cmd_buffer->state.pending_pipe_bits |=
- ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_CS_STALL_BIT;
+ ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_END_OF_PIPE_SYNC_BIT;
switch (ccs_op) {
case ISL_AUX_OP_FAST_CLEAR:
- blorp_fast_clear(&batch, &surf, format,
+ blorp_fast_clear(&batch, &surf, format, swizzle,
level, base_layer, layer_count,
0, 0, level_width, level_height);
break;
}
cmd_buffer->state.pending_pipe_bits |=
- ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_CS_STALL_BIT;
+ ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT | ANV_PIPE_END_OF_PIPE_SYNC_BIT;
blorp_batch_finish(&batch);
}