winsys/amdgpu: avoid ioctl call when fence_wait is called without timeout
[mesa.git] / src / intel / vulkan / anv_formats.c
index 233abc1882e9d3f6862c4c22bfa6026ea908fa80..b52c7ca20f4fbcb6f3ebbca37d3584935d70d048 100644 (file)
@@ -246,8 +246,8 @@ static const struct anv_format anv_formats[] = {
  * Exactly one bit must be set in \a aspect.
  */
 struct anv_format
-anv_get_format(VkFormat vk_format, VkImageAspectFlags aspect,
-               VkImageTiling tiling)
+anv_get_format(const struct brw_device_info *devinfo, VkFormat vk_format,
+               VkImageAspectFlags aspect, VkImageTiling tiling)
 {
    struct anv_format format = anv_formats[vk_format];
 
@@ -287,6 +287,16 @@ anv_get_format(VkFormat vk_format, VkImageAspectFlags aspect,
       }
    }
 
+   /* The B4G4R4A4 format isn't available prior to Sky Lake so we have to fall
+    * back to a format with a more complex swizzle.
+    */
+   if (vk_format == VK_FORMAT_B4G4R4A4_UNORM_PACK16 && devinfo->gen < 9) {
+      return (struct anv_format) {
+         .isl_format = ISL_FORMAT_B4G4R4A4_UNORM,
+         .swizzle = ISL_SWIZZLE(GREEN, RED, ALPHA, BLUE),
+      };
+   }
+
    return format;
 }
 
@@ -382,9 +392,11 @@ anv_physical_device_get_format_properties(struct anv_physical_device *physical_d
                VK_FORMAT_FEATURE_BLIT_DST_BIT;
    } else {
       struct anv_format linear_fmt, tiled_fmt;
-      linear_fmt = anv_get_format(format, VK_IMAGE_ASPECT_COLOR_BIT,
+      linear_fmt = anv_get_format(physical_device->info, format,
+                                  VK_IMAGE_ASPECT_COLOR_BIT,
                                   VK_IMAGE_TILING_LINEAR);
-      tiled_fmt = anv_get_format(format, VK_IMAGE_ASPECT_COLOR_BIT,
+      tiled_fmt = anv_get_format(physical_device->info, format,
+                                 VK_IMAGE_ASPECT_COLOR_BIT,
                                  VK_IMAGE_TILING_OPTIMAL);
 
       linear = get_image_format_properties(gen, linear_fmt.isl_format,