winsys/amdgpu: avoid ioctl call when fence_wait is called without timeout
[mesa.git] / src / intel / vulkan / anv_formats.c
index 4d5d3ceb598449b72e649e036f2992bcd7f93375..b52c7ca20f4fbcb6f3ebbca37d3584935d70d048 100644 (file)
 #include "brw_surface_formats.h"
 #include "vk_format_info.h"
 
-#define RGBA { 0, 1, 2, 3 }
-#define BGRA { 2, 1, 0, 3 }
+#define ISL_SWIZZLE(r, g, b, a) { \
+   ISL_CHANNEL_SELECT_##r, \
+   ISL_CHANNEL_SELECT_##g, \
+   ISL_CHANNEL_SELECT_##b, \
+   ISL_CHANNEL_SELECT_##a, \
+}
+
+#define RGBA ISL_SWIZZLE(RED, GREEN, BLUE, ALPHA)
+#define BGRA ISL_SWIZZLE(BLUE, GREEN, RED, ALPHA)
+#define RGB1 ISL_SWIZZLE(RED, GREEN, BLUE, ONE)
 
 #define swiz_fmt(__vk_fmt, __hw_fmt, __swizzle)     \
    [__vk_fmt] = { \
@@ -238,49 +246,58 @@ static const struct anv_format anv_formats[] = {
  * Exactly one bit must be set in \a aspect.
  */
 struct anv_format
-anv_get_format(VkFormat vk_format, VkImageAspectFlags aspect,
-               VkImageTiling tiling)
+anv_get_format(const struct brw_device_info *devinfo, VkFormat vk_format,
+               VkImageAspectFlags aspect, VkImageTiling tiling)
 {
    struct anv_format format = anv_formats[vk_format];
 
-   const struct isl_format_layout *isl_layout =
-      isl_format_get_layout(format.isl_format);
-
-   switch (aspect) {
-   case VK_IMAGE_ASPECT_COLOR_BIT:
-      if (format.isl_format == ISL_FORMAT_UNSUPPORTED) {
-         return format;
-      } else if (tiling == VK_IMAGE_TILING_OPTIMAL &&
-                 !util_is_power_of_two(isl_layout->bs)) {
-         /* Tiled formats *must* be power-of-two because we need up upload
-          * them with the render pipeline.  For 3-channel formats, we fix
-          * this by switching them over to RGBX or RGBA formats under the
-          * hood.
-          */
-         enum isl_format rgbx = isl_format_rgb_to_rgbx(format.isl_format);
-         if (rgbx != ISL_FORMAT_UNSUPPORTED)
-            format.isl_format = rgbx;
-         else
-            format.isl_format = isl_format_rgb_to_rgba(format.isl_format);
-         return format;
-      } else {
-         return format;
-      }
-
-   case VK_IMAGE_ASPECT_DEPTH_BIT:
-   case (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT):
-      assert(vk_format_aspects(vk_format) & VK_IMAGE_ASPECT_DEPTH_BIT);
+   if (format.isl_format == ISL_FORMAT_UNSUPPORTED)
       return format;
 
-   case VK_IMAGE_ASPECT_STENCIL_BIT:
+   if (aspect == VK_IMAGE_ASPECT_STENCIL_BIT) {
       assert(vk_format_aspects(vk_format) & VK_IMAGE_ASPECT_STENCIL_BIT);
       format.isl_format = ISL_FORMAT_R8_UINT;
       return format;
+   }
 
-   default:
-      unreachable("bad VkImageAspect");
+   if (aspect & VK_IMAGE_ASPECT_DEPTH_BIT) {
+      assert(vk_format_aspects(vk_format) & VK_IMAGE_ASPECT_DEPTH_BIT);
       return format;
    }
+
+   assert(aspect == VK_IMAGE_ASPECT_COLOR_BIT);
+   assert(vk_format_aspects(vk_format) == VK_IMAGE_ASPECT_COLOR_BIT);
+
+   const struct isl_format_layout *isl_layout =
+      isl_format_get_layout(format.isl_format);
+
+   if (tiling == VK_IMAGE_TILING_OPTIMAL &&
+       !util_is_power_of_two(isl_layout->bs)) {
+      /* Tiled formats *must* be power-of-two because we need up upload
+       * them with the render pipeline.  For 3-channel formats, we fix
+       * this by switching them over to RGBX or RGBA formats under the
+       * hood.
+       */
+      enum isl_format rgbx = isl_format_rgb_to_rgbx(format.isl_format);
+      if (rgbx != ISL_FORMAT_UNSUPPORTED) {
+         format.isl_format = rgbx;
+      } else {
+         format.isl_format = isl_format_rgb_to_rgba(format.isl_format);
+         format.swizzle = (struct anv_format_swizzle) RGB1;
+      }
+   }
+
+   /* The B4G4R4A4 format isn't available prior to Sky Lake so we have to fall
+    * back to a format with a more complex swizzle.
+    */
+   if (vk_format == VK_FORMAT_B4G4R4A4_UNORM_PACK16 && devinfo->gen < 9) {
+      return (struct anv_format) {
+         .isl_format = ISL_FORMAT_B4G4R4A4_UNORM,
+         .swizzle = ISL_SWIZZLE(GREEN, RED, ALPHA, BLUE),
+      };
+   }
+
+   return format;
 }
 
 // Format capabilities
@@ -308,13 +325,16 @@ get_image_format_properties(int gen, enum isl_format base,
     * moved, then blending won't work correctly.  The PRM tells us
     * straight-up not to render to such a surface.
     */
-   if (info->render_target <= gen && format.swizzle.a == 3) {
+   if (info->render_target <= gen &&
+       format.swizzle.a == ISL_CHANNEL_SELECT_ALPHA) {
       flags |= VK_FORMAT_FEATURE_COLOR_ATTACHMENT_BIT |
                VK_FORMAT_FEATURE_BLIT_DST_BIT;
    }
 
-   if (info->alpha_blend <= gen && format.swizzle.a == 3)
+   if (info->alpha_blend <= gen &&
+       format.swizzle.a == ISL_CHANNEL_SELECT_ALPHA) {
       flags |= VK_FORMAT_FEATURE_COLOR_ATTACHMENT_BLEND_BIT;
+   }
 
    /* Load/store is determined based on base format.  This prevents RGB
     * formats from showing up as load/store capable.
@@ -372,9 +392,11 @@ anv_physical_device_get_format_properties(struct anv_physical_device *physical_d
                VK_FORMAT_FEATURE_BLIT_DST_BIT;
    } else {
       struct anv_format linear_fmt, tiled_fmt;
-      linear_fmt = anv_get_format(format, VK_IMAGE_ASPECT_COLOR_BIT,
+      linear_fmt = anv_get_format(physical_device->info, format,
+                                  VK_IMAGE_ASPECT_COLOR_BIT,
                                   VK_IMAGE_TILING_LINEAR);
-      tiled_fmt = anv_get_format(format, VK_IMAGE_ASPECT_COLOR_BIT,
+      tiled_fmt = anv_get_format(physical_device->info, format,
+                                 VK_IMAGE_ASPECT_COLOR_BIT,
                                  VK_IMAGE_TILING_OPTIMAL);
 
       linear = get_image_format_properties(gen, linear_fmt.isl_format,