#include <string.h>
#include <unistd.h>
#include <fcntl.h>
+#include <sys/mman.h>
#include "anv_private.h"
#include "util/debug.h"
+#include "vk_util.h"
#include "vk_format_info.h"
-/**
- * Exactly one bit must be set in \a aspect.
- */
static isl_surf_usage_flags_t
-choose_isl_surf_usage(VkImageUsageFlags vk_usage,
- VkImageAspectFlags aspect)
+choose_isl_surf_usage(VkImageCreateFlags vk_create_flags,
+ VkImageUsageFlags vk_usage,
+ isl_surf_usage_flags_t isl_extra_usage,
+ VkImageAspectFlagBits aspect)
{
- isl_surf_usage_flags_t isl_usage = 0;
+ isl_surf_usage_flags_t isl_usage = isl_extra_usage;
if (vk_usage & VK_IMAGE_USAGE_SAMPLED_BIT)
isl_usage |= ISL_SURF_USAGE_TEXTURE_BIT;
if (vk_usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT)
isl_usage |= ISL_SURF_USAGE_RENDER_TARGET_BIT;
- if (vk_usage & VK_IMAGE_CREATE_CUBE_COMPATIBLE_BIT)
+ if (vk_create_flags & VK_IMAGE_CREATE_CUBE_COMPATIBLE_BIT)
isl_usage |= ISL_SURF_USAGE_CUBE_BIT;
/* Even if we're only using it for transfer operations, clears to depth and
isl_usage |= ISL_SURF_USAGE_STENCIL_BIT;
break;
case VK_IMAGE_ASPECT_COLOR_BIT:
+ case VK_IMAGE_ASPECT_PLANE_0_BIT_KHR:
+ case VK_IMAGE_ASPECT_PLANE_1_BIT_KHR:
+ case VK_IMAGE_ASPECT_PLANE_2_BIT_KHR:
break;
default:
unreachable("bad VkImageAspect");
return isl_usage;
}
-/**
- * Exactly one bit must be set in \a aspect.
- */
static struct anv_surface *
-get_surface(struct anv_image *image, VkImageAspectFlags aspect)
+get_surface(struct anv_image *image, VkImageAspectFlagBits aspect)
{
- switch (aspect) {
- default:
- unreachable("bad VkImageAspect");
- case VK_IMAGE_ASPECT_COLOR_BIT:
- return &image->color_surface;
- case VK_IMAGE_ASPECT_DEPTH_BIT:
- return &image->depth_surface;
- case VK_IMAGE_ASPECT_STENCIL_BIT:
- return &image->stencil_surface;
- }
+ uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
+ return &image->planes[plane].surface;
}
static void
-add_surface(struct anv_image *image, struct anv_surface *surf)
+add_surface(struct anv_image *image, struct anv_surface *surf, uint32_t plane)
{
assert(surf->isl.size > 0); /* isl surface must be initialized */
- surf->offset = align_u32(image->size, surf->isl.alignment);
+ if (image->disjoint) {
+ surf->offset = align_u32(image->planes[plane].size, surf->isl.alignment);
+ /* Plane offset is always 0 when it's disjoint. */
+ } else {
+ surf->offset = align_u32(image->size, surf->isl.alignment);
+ /* Determine plane's offset only once when the first surface is added. */
+ if (image->planes[plane].size == 0)
+ image->planes[plane].offset = image->size;
+ }
+
image->size = surf->offset + surf->isl.size;
+ image->planes[plane].size = (surf->offset + surf->isl.size) - image->planes[plane].offset;
+
image->alignment = MAX2(image->alignment, surf->isl.alignment);
+ image->planes[plane].alignment = MAX2(image->planes[plane].alignment,
+ surf->isl.alignment);
+}
+
+
+static bool
+all_formats_ccs_e_compatible(const struct gen_device_info *devinfo,
+ const struct VkImageCreateInfo *vk_info)
+{
+ enum isl_format format =
+ anv_get_isl_format(devinfo, vk_info->format,
+ VK_IMAGE_ASPECT_COLOR_BIT, vk_info->tiling);
+
+ if (!isl_format_supports_ccs_e(devinfo, format))
+ return false;
+
+ if (!(vk_info->flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT))
+ return true;
+
+ const VkImageFormatListCreateInfoKHR *fmt_list =
+ vk_find_struct_const(vk_info->pNext, IMAGE_FORMAT_LIST_CREATE_INFO_KHR);
+
+ if (!fmt_list || fmt_list->viewFormatCount == 0)
+ return false;
+
+ for (uint32_t i = 0; i < fmt_list->viewFormatCount; i++) {
+ enum isl_format view_format =
+ anv_get_isl_format(devinfo, fmt_list->pViewFormats[i],
+ VK_IMAGE_ASPECT_COLOR_BIT, vk_info->tiling);
+
+ if (!isl_formats_are_ccs_e_compatible(devinfo, format, view_format))
+ return false;
+ }
+
+ return true;
+}
+
+/**
+ * For color images that have an auxiliary surface, request allocation for an
+ * additional buffer that mainly stores fast-clear values. Use of this buffer
+ * allows us to access the image's subresources while being aware of their
+ * fast-clear values in non-trivial cases (e.g., outside of a render pass in
+ * which a fast clear has occurred).
+ *
+ * For the purpose of discoverability, the algorithm used to manage this buffer
+ * is described here. A clear value in this buffer is updated when a fast clear
+ * is performed on a subresource. One of two synchronization operations is
+ * performed in order for a following memory access to use the fast-clear
+ * value:
+ * a. Copy the value from the buffer to the surface state object used for
+ * reading. This is done implicitly when the value is the clear value
+ * predetermined to be the default in other surface state objects. This
+ * is currently only done explicitly for the operation below.
+ * b. Do (a) and use the surface state object to resolve the subresource.
+ * This is only done during layout transitions for decent performance.
+ *
+ * With the above scheme, we can fast-clear whenever the hardware allows except
+ * for two cases in which synchronization becomes impossible or undesirable:
+ * * The subresource is in the GENERAL layout and is cleared to a value
+ * other than the special default value.
+ *
+ * Performing a synchronization operation in order to read from the
+ * subresource is undesirable in this case. Firstly, b) is not an option
+ * because a layout transition isn't required between a write and read of
+ * an image in the GENERAL layout. Secondly, it's undesirable to do a)
+ * explicitly because it would require large infrastructural changes. The
+ * Vulkan API supports us in deciding not to optimize this layout by
+ * stating that using this layout may cause suboptimal performance. NOTE:
+ * the auxiliary buffer must always be enabled to support a) implicitly.
+ *
+ *
+ * * For the given miplevel, only some of the layers are cleared at once.
+ *
+ * If the user clears each layer to a different value, then tries to
+ * render to multiple layers at once, we have no ability to perform a
+ * synchronization operation in between. a) is not helpful because the
+ * object can only hold one clear value. b) is not an option because a
+ * layout transition isn't required in this case.
+ */
+static void
+add_fast_clear_state_buffer(struct anv_image *image,
+ VkImageAspectFlagBits aspect,
+ uint32_t plane,
+ const struct anv_device *device)
+{
+ assert(image && device);
+ assert(image->planes[plane].aux_surface.isl.size > 0 &&
+ image->aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV);
+
+ /* The offset to the buffer of clear values must be dword-aligned for GPU
+ * memcpy operations. It is located immediately after the auxiliary surface.
+ */
+
+ /* Tiled images are guaranteed to be 4K aligned, so the image alignment
+ * should also be dword-aligned.
+ */
+ assert(image->alignment % 4 == 0);
+
+ /* Auxiliary buffers should be a multiple of 4K, so the start of the clear
+ * values buffer should already be dword-aligned.
+ */
+ assert((image->planes[plane].offset + image->planes[plane].size) % 4 == 0);
+
+ /* This buffer should be at the very end of the plane. */
+ if (image->disjoint) {
+ assert(image->planes[plane].size ==
+ (image->planes[plane].offset + image->planes[plane].size));
+ } else {
+ assert(image->size ==
+ (image->planes[plane].offset + image->planes[plane].size));
+ }
+
+ const unsigned entry_size = anv_fast_clear_state_entry_size(device);
+ /* There's no padding between entries, so ensure that they're always a
+ * multiple of 32 bits in order to enable GPU memcpy operations.
+ */
+ assert(entry_size % 4 == 0);
+
+ const unsigned plane_state_size =
+ entry_size * anv_image_aux_levels(image, aspect);
+
+ image->planes[plane].fast_clear_state_offset =
+ image->planes[plane].offset + image->planes[plane].size;
+
+ image->planes[plane].size += plane_state_size;
+ image->size += plane_state_size;
}
/**
* Initialize the anv_image::*_surface selected by \a aspect. Then update the
* image's memory requirements (that is, the image's size and alignment).
- *
- * Exactly one bit must be set in \a aspect.
*/
static VkResult
make_surface(const struct anv_device *dev,
struct anv_image *image,
const struct anv_image_create_info *anv_info,
- VkImageAspectFlags aspect)
+ VkImageAspectFlagBits aspect)
{
const VkImageCreateInfo *vk_info = anv_info->vk_info;
bool ok UNUSED;
assert(tiling_flags);
- struct anv_surface *anv_surf = get_surface(image, aspect);
-
image->extent = anv_sanitize_image_extent(vk_info->imageType,
vk_info->extent);
- enum isl_format format = anv_get_isl_format(&dev->info, vk_info->format,
- aspect, vk_info->tiling);
- assert(format != ISL_FORMAT_UNSUPPORTED);
+ const unsigned plane = anv_image_aspect_to_plane(image->aspects, aspect);
+ const struct anv_format_plane plane_format =
+ anv_get_format_plane(&dev->info, image->vk_format, aspect, image->tiling);
+ struct anv_surface *anv_surf = &image->planes[plane].surface;
+
+ const isl_surf_usage_flags_t usage =
+ choose_isl_surf_usage(vk_info->flags, image->usage,
+ anv_info->isl_extra_usage_flags, aspect);
+
+ /* If an image is created as BLOCK_TEXEL_VIEW_COMPATIBLE, then we need to
+ * fall back to linear on Broadwell and earlier because we aren't
+ * guaranteed that we can handle offsets correctly. On Sky Lake, the
+ * horizontal and vertical alignments are sufficiently high that we can
+ * just use RENDER_SURFACE_STATE::X/Y Offset.
+ */
+ bool needs_shadow = false;
+ if (dev->info.gen <= 8 &&
+ (vk_info->flags & VK_IMAGE_CREATE_BLOCK_TEXEL_VIEW_COMPATIBLE_BIT_KHR) &&
+ vk_info->tiling == VK_IMAGE_TILING_OPTIMAL) {
+ assert(isl_format_is_compressed(plane_format.isl_format));
+ tiling_flags = ISL_TILING_LINEAR_BIT;
+ needs_shadow = true;
+ }
ok = isl_surf_init(&dev->isl_dev, &anv_surf->isl,
.dim = vk_to_isl_surf_dim[vk_info->imageType],
- .format = format,
- .width = image->extent.width,
- .height = image->extent.height,
+ .format = plane_format.isl_format,
+ .width = image->extent.width / plane_format.denominator_scales[0],
+ .height = image->extent.height / plane_format.denominator_scales[1],
.depth = image->extent.depth,
.levels = vk_info->mipLevels,
.array_len = vk_info->arrayLayers,
.samples = vk_info->samples,
.min_alignment = 0,
.row_pitch = anv_info->stride,
- .usage = choose_isl_surf_usage(image->usage, aspect),
+ .usage = usage,
.tiling_flags = tiling_flags);
/* isl_surf_init() will fail only if provided invalid input. Invalid input
*/
assert(ok);
- add_surface(image, anv_surf);
+ image->planes[plane].aux_usage = ISL_AUX_USAGE_NONE;
+
+ add_surface(image, anv_surf, plane);
+
+ /* If an image is created as BLOCK_TEXEL_VIEW_COMPATIBLE, then we need to
+ * create an identical tiled shadow surface for use while texturing so we
+ * don't get garbage performance.
+ */
+ if (needs_shadow) {
+ assert(aspect == VK_IMAGE_ASPECT_COLOR_BIT);
+ assert(tiling_flags == ISL_TILING_LINEAR_BIT);
+
+ ok = isl_surf_init(&dev->isl_dev, &image->planes[plane].shadow_surface.isl,
+ .dim = vk_to_isl_surf_dim[vk_info->imageType],
+ .format = plane_format.isl_format,
+ .width = image->extent.width,
+ .height = image->extent.height,
+ .depth = image->extent.depth,
+ .levels = vk_info->mipLevels,
+ .array_len = vk_info->arrayLayers,
+ .samples = vk_info->samples,
+ .min_alignment = 0,
+ .row_pitch = anv_info->stride,
+ .usage = usage,
+ .tiling_flags = ISL_TILING_ANY_MASK);
+
+ /* isl_surf_init() will fail only if provided invalid input. Invalid input
+ * is illegal in Vulkan.
+ */
+ assert(ok);
+
+ add_surface(image, &image->planes[plane].shadow_surface, plane);
+ }
/* Add a HiZ surface to a depth buffer that will be used for rendering.
*/
if (!(image->usage & VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) {
/* It will never be used as an attachment, HiZ is pointless. */
} else if (dev->info.gen == 7) {
- anv_perf_warn("Implement gen7 HiZ");
+ anv_perf_warn(dev->instance, image, "Implement gen7 HiZ");
} else if (vk_info->mipLevels > 1) {
- anv_perf_warn("Enable multi-LOD HiZ");
+ anv_perf_warn(dev->instance, image, "Enable multi-LOD HiZ");
} else if (vk_info->arrayLayers > 1) {
- anv_perf_warn("Implement multi-arrayLayer HiZ clears and resolves");
+ anv_perf_warn(dev->instance, image,
+ "Implement multi-arrayLayer HiZ clears and resolves");
} else if (dev->info.gen == 8 && vk_info->samples > 1) {
- anv_perf_warn("Enable gen8 multisampled HiZ");
+ anv_perf_warn(dev->instance, image, "Enable gen8 multisampled HiZ");
} else if (!unlikely(INTEL_DEBUG & DEBUG_NO_HIZ)) {
- assert(image->aux_surface.isl.size == 0);
- ok = isl_surf_get_hiz_surf(&dev->isl_dev, &image->depth_surface.isl,
- &image->aux_surface.isl);
+ assert(image->planes[plane].aux_surface.isl.size == 0);
+ ok = isl_surf_get_hiz_surf(&dev->isl_dev,
+ &image->planes[plane].surface.isl,
+ &image->planes[plane].aux_surface.isl);
assert(ok);
- add_surface(image, &image->aux_surface);
- image->aux_usage = ISL_AUX_USAGE_HIZ;
+ add_surface(image, &image->planes[plane].aux_surface, plane);
+ image->planes[plane].aux_usage = ISL_AUX_USAGE_HIZ;
}
- } else if (aspect == VK_IMAGE_ASPECT_COLOR_BIT && vk_info->samples == 1) {
- if (!unlikely(INTEL_DEBUG & DEBUG_NO_RBC)) {
- assert(image->aux_surface.isl.size == 0);
- ok = isl_surf_get_ccs_surf(&dev->isl_dev, &anv_surf->isl,
- &image->aux_surface.isl);
+ } else if ((aspect & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) && vk_info->samples == 1) {
+ /* TODO: Disallow compression with :
+ *
+ * 1) non multiplanar images (We appear to hit a sampler bug with
+ * CCS & R16G16 format. Putting the clear state a page/4096bytes
+ * further fixes the issue).
+ *
+ * 2) alias images, because they might be aliases of images
+ * described in 1)
+ *
+ * 3) compression disabled by debug
+ */
+ const bool allow_compression =
+ image->n_planes == 1 &&
+ (vk_info->flags & VK_IMAGE_CREATE_ALIAS_BIT_KHR) == 0 &&
+ likely((INTEL_DEBUG & DEBUG_NO_RBC) == 0);
+
+ if (allow_compression) {
+ assert(image->planes[plane].aux_surface.isl.size == 0);
+ ok = isl_surf_get_ccs_surf(&dev->isl_dev,
+ &image->planes[plane].surface.isl,
+ &image->planes[plane].aux_surface.isl, 0);
if (ok) {
- add_surface(image, &image->aux_surface);
+
+ /* Disable CCS when it is not useful (i.e., when you can't render
+ * to the image with CCS enabled).
+ */
+ if (!isl_format_supports_rendering(&dev->info,
+ plane_format.isl_format)) {
+ /* While it may be technically possible to enable CCS for this
+ * image, we currently don't have things hooked up to get it
+ * working.
+ */
+ anv_perf_warn(dev->instance, image,
+ "This image format doesn't support rendering. "
+ "Not allocating an CCS buffer.");
+ image->planes[plane].aux_surface.isl.size = 0;
+ return VK_SUCCESS;
+ }
+
+ add_surface(image, &image->planes[plane].aux_surface, plane);
+ add_fast_clear_state_buffer(image, aspect, plane, dev);
/* For images created without MUTABLE_FORMAT_BIT set, we know that
* they will always be used with the original format. In
* compression on at all times for these formats.
*/
if (!(vk_info->usage & VK_IMAGE_USAGE_STORAGE_BIT) &&
- !(vk_info->flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT) &&
- isl_format_supports_ccs_e(&dev->info, format)) {
- image->aux_usage = ISL_AUX_USAGE_CCS_E;
+ all_formats_ccs_e_compatible(&dev->info, vk_info)) {
+ image->planes[plane].aux_usage = ISL_AUX_USAGE_CCS_E;
}
}
}
- } else if (aspect == VK_IMAGE_ASPECT_COLOR_BIT && vk_info->samples > 1) {
- assert(image->aux_surface.isl.size == 0);
+ } else if ((aspect & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) && vk_info->samples > 1) {
assert(!(vk_info->usage & VK_IMAGE_USAGE_STORAGE_BIT));
- ok = isl_surf_get_mcs_surf(&dev->isl_dev, &anv_surf->isl,
- &image->aux_surface.isl);
+ assert(image->planes[plane].aux_surface.isl.size == 0);
+ ok = isl_surf_get_mcs_surf(&dev->isl_dev,
+ &image->planes[plane].surface.isl,
+ &image->planes[plane].aux_surface.isl);
if (ok) {
- add_surface(image, &image->aux_surface);
- image->aux_usage = ISL_AUX_USAGE_MCS;
+ add_surface(image, &image->planes[plane].aux_surface, plane);
+ add_fast_clear_state_buffer(image, aspect, plane, dev);
+ image->planes[plane].aux_usage = ISL_AUX_USAGE_MCS;
}
}
+ assert((image->planes[plane].offset + image->planes[plane].size) == image->size);
+
+ /* Upper bound of the last surface should be smaller than the plane's
+ * size.
+ */
+ assert((MAX2(image->planes[plane].surface.offset,
+ image->planes[plane].aux_surface.offset) +
+ (image->planes[plane].aux_surface.isl.size > 0 ?
+ image->planes[plane].aux_surface.isl.size :
+ image->planes[plane].surface.isl.size)) <=
+ (image->planes[plane].offset + image->planes[plane].size));
+
+ if (image->planes[plane].aux_surface.isl.size) {
+ /* assert(image->planes[plane].fast_clear_state_offset == */
+ /* (image->planes[plane].aux_surface.offset + image->planes[plane].aux_surface.isl.size)); */
+ assert(image->planes[plane].fast_clear_state_offset <
+ (image->planes[plane].offset + image->planes[plane].size));
+ }
+
return VK_SUCCESS;
}
anv_assert(pCreateInfo->extent.height > 0);
anv_assert(pCreateInfo->extent.depth > 0);
- image = vk_alloc2(&device->alloc, alloc, sizeof(*image), 8,
- VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
+ image = vk_zalloc2(&device->alloc, alloc, sizeof(*image), 8,
+ VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
if (!image)
return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
- memset(image, 0, sizeof(*image));
image->type = pCreateInfo->imageType;
image->extent = pCreateInfo->extent;
image->vk_format = pCreateInfo->format;
+ image->format = anv_get_format(pCreateInfo->format);
image->aspects = vk_format_aspects(image->vk_format);
image->levels = pCreateInfo->mipLevels;
image->array_size = pCreateInfo->arrayLayers;
image->samples = pCreateInfo->samples;
image->usage = pCreateInfo->usage;
image->tiling = pCreateInfo->tiling;
- image->aux_usage = ISL_AUX_USAGE_NONE;
+ image->disjoint = pCreateInfo->flags & VK_IMAGE_CREATE_DISJOINT_BIT_KHR;
+
+ const struct anv_format *format = anv_get_format(image->vk_format);
+ assert(format != NULL);
+
+ image->n_planes = format->n_planes;
uint32_t b;
for_each_bit(b, image->aspects) {
const VkAllocationCallbacks *pAllocator,
VkImage *pImage)
{
+#ifdef ANDROID
+ const VkNativeBufferANDROID *gralloc_info =
+ vk_find_struct_const(pCreateInfo->pNext, NATIVE_BUFFER_ANDROID);
+
+ if (gralloc_info)
+ return anv_image_from_gralloc(device, pCreateInfo, gralloc_info,
+ pAllocator, pImage);
+#endif
+
return anv_image_create(device,
&(struct anv_image_create_info) {
.vk_info = pCreateInfo,
if (!image)
return;
+ for (uint32_t p = 0; p < image->n_planes; ++p) {
+ if (image->planes[p].bo_is_owned) {
+ assert(image->planes[p].bo != NULL);
+ anv_bo_cache_release(device, &device->bo_cache, image->planes[p].bo);
+ }
+ }
+
vk_free2(&device->alloc, pAllocator, image);
}
+static void anv_image_bind_memory_plane(struct anv_device *device,
+ struct anv_image *image,
+ uint32_t plane,
+ struct anv_device_memory *memory,
+ uint32_t memory_offset)
+{
+ assert(!image->planes[plane].bo_is_owned);
+
+ if (!memory) {
+ image->planes[plane].bo = NULL;
+ image->planes[plane].bo_offset = 0;
+ return;
+ }
+
+ image->planes[plane].bo = memory->bo;
+ image->planes[plane].bo_offset = memory_offset;
+}
+
VkResult anv_BindImageMemory(
VkDevice _device,
VkImage _image,
ANV_FROM_HANDLE(anv_device_memory, mem, _memory);
ANV_FROM_HANDLE(anv_image, image, _image);
- if (mem == NULL) {
- image->bo = NULL;
- image->offset = 0;
- return VK_SUCCESS;
+ uint32_t aspect_bit;
+ anv_foreach_image_aspect_bit(aspect_bit, image, image->aspects) {
+ uint32_t plane =
+ anv_image_aspect_to_plane(image->aspects, 1UL << aspect_bit);
+ anv_image_bind_memory_plane(device, image, plane, mem, memoryOffset);
}
- image->bo = &mem->bo;
- image->offset = memoryOffset;
+ return VK_SUCCESS;
+}
- if (image->aux_surface.isl.size > 0) {
+VkResult anv_BindImageMemory2KHR(
+ VkDevice _device,
+ uint32_t bindInfoCount,
+ const VkBindImageMemoryInfoKHR* pBindInfos)
+{
+ ANV_FROM_HANDLE(anv_device, device, _device);
- /* The offset and size must be a multiple of 4K or else the
- * anv_gem_mmap call below will return NULL.
- */
- assert((image->offset + image->aux_surface.offset) % 4096 == 0);
- assert(image->aux_surface.isl.size % 4096 == 0);
-
- /* Auxiliary surfaces need to have their memory cleared to 0 before they
- * can be used. For CCS surfaces, this puts them in the "resolved"
- * state so they can be used with CCS enabled before we ever touch it
- * from the GPU. For HiZ, we need something valid or else we may get
- * GPU hangs on some hardware and 0 works fine.
- */
- void *map = anv_gem_mmap(device, image->bo->gem_handle,
- image->offset + image->aux_surface.offset,
- image->aux_surface.isl.size,
- device->info.has_llc ? 0 : I915_MMAP_WC);
+ for (uint32_t i = 0; i < bindInfoCount; i++) {
+ const VkBindImageMemoryInfoKHR *bind_info = &pBindInfos[i];
+ ANV_FROM_HANDLE(anv_device_memory, mem, bind_info->memory);
+ ANV_FROM_HANDLE(anv_image, image, bind_info->image);
+ VkImageAspectFlags aspects = image->aspects;
- /* If anv_gem_mmap returns NULL, it's likely that the kernel was
- * not able to find space on the host to create a proper mapping.
- */
- if (map == NULL)
- return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
+ vk_foreach_struct_const(s, bind_info->pNext) {
+ switch (s->sType) {
+ case VK_STRUCTURE_TYPE_BIND_IMAGE_PLANE_MEMORY_INFO_KHR: {
+ const VkBindImagePlaneMemoryInfoKHR *plane_info =
+ (const VkBindImagePlaneMemoryInfoKHR *) s;
- memset(map, 0, image->aux_surface.isl.size);
+ aspects = plane_info->planeAspect;
+ break;
+ }
+ default:
+ anv_debug_ignored_stype(s->sType);
+ break;
+ }
+ }
- anv_gem_munmap(map, image->aux_surface.isl.size);
+ uint32_t aspect_bit;
+ anv_foreach_image_aspect_bit(aspect_bit, image, aspects) {
+ uint32_t plane =
+ anv_image_aspect_to_plane(image->aspects, 1UL << aspect_bit);
+ anv_image_bind_memory_plane(device, image, plane,
+ mem, bind_info->memoryOffset);
+ }
}
return VK_SUCCESS;
assert(__builtin_popcount(pSubresource->aspectMask) == 1);
- switch (pSubresource->aspectMask) {
- case VK_IMAGE_ASPECT_COLOR_BIT:
- anv_surface_get_subresource_layout(image, &image->color_surface,
- pSubresource, pLayout);
- break;
- case VK_IMAGE_ASPECT_DEPTH_BIT:
- anv_surface_get_subresource_layout(image, &image->depth_surface,
- pSubresource, pLayout);
- break;
- case VK_IMAGE_ASPECT_STENCIL_BIT:
- anv_surface_get_subresource_layout(image, &image->stencil_surface,
- pSubresource, pLayout);
- break;
- default:
- assert(!"Invalid image aspect");
- }
+ anv_surface_get_subresource_layout(image,
+ get_surface(image,
+ pSubresource->aspectMask),
+ pSubresource, pLayout);
}
/**
- * This function determines the optimal buffer to use for device
- * accesses given a VkImageLayout and other pieces of information needed to
- * make that determination. This does not determine the optimal buffer to
- * use during a resolve operation.
- *
- * NOTE: Some layouts do not support device access.
+ * This function determines the optimal buffer to use for a given
+ * VkImageLayout and other pieces of information needed to make that
+ * determination. This does not determine the optimal buffer to use
+ * during a resolve operation.
*
* @param devinfo The device information of the Intel GPU.
* @param image The image that may contain a collection of buffers.
- * @param aspects The aspect(s) of the image to be accessed.
+ * @param plane The plane of the image to be accessed.
* @param layout The current layout of the image aspect(s).
*
* @return The primary buffer that should be used for the given layout.
enum isl_aux_usage
anv_layout_to_aux_usage(const struct gen_device_info * const devinfo,
const struct anv_image * const image,
- const VkImageAspectFlags aspects,
+ const VkImageAspectFlagBits aspect,
const VkImageLayout layout)
{
/* Validate the inputs. */
/* The layout of a NULL image is not properly defined. */
assert(image != NULL);
- /* The aspects must be a subset of the image aspects. */
- assert(aspects & image->aspects && aspects <= image->aspects);
+ /* The aspect must be exactly one of the image aspects. */
+ assert(_mesa_bitcount(aspect) == 1 && (aspect & image->aspects));
/* Determine the optimal buffer. */
+ uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
+
/* If there is no auxiliary surface allocated, we must use the one and only
* main buffer.
*/
- if (image->aux_surface.isl.size == 0)
+ if (image->planes[plane].aux_surface.isl.size == 0)
return ISL_AUX_USAGE_NONE;
/* All images that use an auxiliary surface are required to be tiled. */
assert(image->tiling == VK_IMAGE_TILING_OPTIMAL);
- /* On BDW+, when clearing the stencil aspect of a depth stencil image,
- * the HiZ buffer allows us to record the clear with a relatively small
- * number of packets. Prior to BDW, the HiZ buffer provides no known benefit
- * to the stencil aspect.
- */
- if (devinfo->gen < 8 && aspects == VK_IMAGE_ASPECT_STENCIL_BIT)
- return ISL_AUX_USAGE_NONE;
-
- const bool color_aspect = aspects == VK_IMAGE_ASPECT_COLOR_BIT;
+ /* Stencil has no aux */
+ assert(aspect != VK_IMAGE_ASPECT_STENCIL_BIT);
/* The following switch currently only handles depth stencil aspects.
* TODO: Handle the color aspect.
*/
- if (color_aspect)
- return image->aux_usage;
+ if (image->aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV)
+ return image->planes[plane].aux_usage;
switch (layout) {
/* Invalid Layouts */
+ case VK_IMAGE_LAYOUT_RANGE_SIZE:
+ case VK_IMAGE_LAYOUT_MAX_ENUM:
+ unreachable("Invalid image layout.");
- /* According to the Vulkan Spec, the following layouts are valid only as
- * initial layouts in a layout transition and don't support device access.
+ /* Undefined layouts
+ *
+ * The pre-initialized layout is equivalent to the undefined layout for
+ * optimally-tiled images. We can only do color compression (CCS or HiZ)
+ * on tiled images.
*/
case VK_IMAGE_LAYOUT_UNDEFINED:
case VK_IMAGE_LAYOUT_PREINITIALIZED:
- case VK_IMAGE_LAYOUT_RANGE_SIZE:
- case VK_IMAGE_LAYOUT_MAX_ENUM:
- unreachable("Invalid image layout for device access.");
+ return ISL_AUX_USAGE_NONE;
/* Transfer Layouts
/* Sampling Layouts */
case VK_IMAGE_LAYOUT_DEPTH_STENCIL_READ_ONLY_OPTIMAL:
- assert(!color_aspect);
+ assert((image->aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) == 0);
/* Fall-through */
case VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL:
- if (anv_can_sample_with_hiz(devinfo, aspects, image->samples))
+ case VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL_KHR:
+ assert(aspect == VK_IMAGE_ASPECT_DEPTH_BIT);
+ if (anv_can_sample_with_hiz(devinfo, image))
return ISL_AUX_USAGE_HIZ;
else
return ISL_AUX_USAGE_NONE;
case VK_IMAGE_LAYOUT_PRESENT_SRC_KHR:
- assert(color_aspect);
+ assert(image->aspects == VK_IMAGE_ASPECT_COLOR_BIT);
/* On SKL+, the render buffer can be decompressed by the presentation
* engine. Support for this feature has not yet landed in the wider
/* Rendering Layouts */
case VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL:
- assert(color_aspect);
+ assert(image->aspects == VK_IMAGE_ASPECT_COLOR_BIT);
unreachable("Color images are not yet supported.");
case VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL:
- assert(!color_aspect);
+ case VK_IMAGE_LAYOUT_DEPTH_ATTACHMENT_STENCIL_READ_ONLY_OPTIMAL_KHR:
+ assert(aspect == VK_IMAGE_ASPECT_DEPTH_BIT);
return ISL_AUX_USAGE_HIZ;
+
+ case VK_IMAGE_LAYOUT_SHARED_PRESENT_KHR:
+ unreachable("VK_KHR_shared_presentable_image is unsupported");
}
/* If the layout isn't recognized in the exhaustive switch above, the
}
}
+void
+anv_image_fill_surface_state(struct anv_device *device,
+ const struct anv_image *image,
+ VkImageAspectFlagBits aspect,
+ const struct isl_view *view_in,
+ isl_surf_usage_flags_t view_usage,
+ enum isl_aux_usage aux_usage,
+ const union isl_color_value *clear_color,
+ enum anv_image_view_state_flags flags,
+ struct anv_surface_state *state_inout,
+ struct brw_image_param *image_param_out)
+{
+ uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
+
+ const struct anv_surface *surface = &image->planes[plane].surface,
+ *aux_surface = &image->planes[plane].aux_surface;
+
+ struct isl_view view = *view_in;
+ view.usage |= view_usage;
+
+ /* For texturing with VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL from a
+ * compressed surface with a shadow surface, we use the shadow instead of
+ * the primary surface. The shadow surface will be tiled, unlike the main
+ * surface, so it should get significantly better performance.
+ */
+ if (image->planes[plane].shadow_surface.isl.size > 0 &&
+ isl_format_is_compressed(view.format) &&
+ (flags & ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL)) {
+ assert(isl_format_is_compressed(surface->isl.format));
+ assert(surface->isl.tiling == ISL_TILING_LINEAR);
+ assert(image->planes[plane].shadow_surface.isl.tiling != ISL_TILING_LINEAR);
+ surface = &image->planes[plane].shadow_surface;
+ }
+
+ if (view_usage == ISL_SURF_USAGE_RENDER_TARGET_BIT)
+ view.swizzle = anv_swizzle_for_render(view.swizzle);
+
+ /* If this is a HiZ buffer we can sample from with a programmable clear
+ * value (SKL+), define the clear value to the optimal constant.
+ */
+ union isl_color_value default_clear_color = { .u32 = { 0, } };
+ if (device->info.gen >= 9 && aux_usage == ISL_AUX_USAGE_HIZ)
+ default_clear_color.f32[0] = ANV_HZ_FC_VAL;
+ if (!clear_color)
+ clear_color = &default_clear_color;
+
+ const uint64_t address = image->planes[plane].bo_offset + surface->offset;
+ const uint64_t aux_address = aux_usage == ISL_AUX_USAGE_NONE ?
+ 0 : (image->planes[plane].bo_offset + aux_surface->offset);
+
+ if (view_usage == ISL_SURF_USAGE_STORAGE_BIT &&
+ !(flags & ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY) &&
+ !isl_has_matching_typed_storage_image_format(&device->info,
+ view.format)) {
+ /* In this case, we are a writeable storage buffer which needs to be
+ * lowered to linear. All tiling and offset calculations will be done in
+ * the shader.
+ */
+ assert(aux_usage == ISL_AUX_USAGE_NONE);
+ isl_buffer_fill_state(&device->isl_dev, state_inout->state.map,
+ .address = address,
+ .size = surface->isl.size,
+ .format = ISL_FORMAT_RAW,
+ .stride = 1,
+ .mocs = device->default_mocs);
+ state_inout->address = address,
+ state_inout->aux_address = 0;
+ } else {
+ if (view_usage == ISL_SURF_USAGE_STORAGE_BIT &&
+ !(flags & ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY)) {
+ /* Typed surface reads support a very limited subset of the shader
+ * image formats. Translate it into the closest format the hardware
+ * supports.
+ */
+ assert(aux_usage == ISL_AUX_USAGE_NONE);
+ view.format = isl_lower_storage_image_format(&device->info,
+ view.format);
+ }
+
+ const struct isl_surf *isl_surf = &surface->isl;
+
+ struct isl_surf tmp_surf;
+ uint32_t offset_B = 0, tile_x_sa = 0, tile_y_sa = 0;
+ if (isl_format_is_compressed(surface->isl.format) &&
+ !isl_format_is_compressed(view.format)) {
+ /* We're creating an uncompressed view of a compressed surface. This
+ * is allowed but only for a single level/layer.
+ */
+ assert(surface->isl.samples == 1);
+ assert(view.levels == 1);
+ assert(view.array_len == 1);
+
+ isl_surf_get_image_surf(&device->isl_dev, isl_surf,
+ view.base_level,
+ surface->isl.dim == ISL_SURF_DIM_3D ?
+ 0 : view.base_array_layer,
+ surface->isl.dim == ISL_SURF_DIM_3D ?
+ view.base_array_layer : 0,
+ &tmp_surf,
+ &offset_B, &tile_x_sa, &tile_y_sa);
+
+ /* The newly created image represents the one subimage we're
+ * referencing with this view so it only has one array slice and
+ * miplevel.
+ */
+ view.base_array_layer = 0;
+ view.base_level = 0;
+
+ /* We're making an uncompressed view here. The image dimensions need
+ * to be scaled down by the block size.
+ */
+ const struct isl_format_layout *fmtl =
+ isl_format_get_layout(surface->isl.format);
+ tmp_surf.format = view.format;
+ tmp_surf.logical_level0_px.width =
+ DIV_ROUND_UP(tmp_surf.logical_level0_px.width, fmtl->bw);
+ tmp_surf.logical_level0_px.height =
+ DIV_ROUND_UP(tmp_surf.logical_level0_px.height, fmtl->bh);
+ tmp_surf.phys_level0_sa.width /= fmtl->bw;
+ tmp_surf.phys_level0_sa.height /= fmtl->bh;
+ tile_x_sa /= fmtl->bw;
+ tile_y_sa /= fmtl->bh;
+
+ isl_surf = &tmp_surf;
+
+ if (device->info.gen <= 8) {
+ assert(surface->isl.tiling == ISL_TILING_LINEAR);
+ assert(tile_x_sa == 0);
+ assert(tile_y_sa == 0);
+ }
+ }
+
+ isl_surf_fill_state(&device->isl_dev, state_inout->state.map,
+ .surf = isl_surf,
+ .view = &view,
+ .address = address + offset_B,
+ .clear_color = *clear_color,
+ .aux_surf = &aux_surface->isl,
+ .aux_usage = aux_usage,
+ .aux_address = aux_address,
+ .mocs = device->default_mocs,
+ .x_offset_sa = tile_x_sa,
+ .y_offset_sa = tile_y_sa);
+ state_inout->address = address + offset_B;
+ if (device->info.gen >= 8) {
+ state_inout->aux_address = aux_address;
+ } else {
+ /* On gen7 and prior, the bottom 12 bits of the MCS base address are
+ * used to store other information. This should be ok, however,
+ * because surface buffer addresses are always 4K page alinged.
+ */
+ uint32_t *aux_addr_dw = state_inout->state.map +
+ device->isl_dev.ss.aux_addr_offset;
+ assert((aux_address & 0xfff) == 0);
+ assert(aux_address == (*aux_addr_dw & 0xfffff000));
+ state_inout->aux_address = *aux_addr_dw;
+ }
+ }
+
+ anv_state_flush(device, state_inout->state);
+
+ if (image_param_out) {
+ assert(view_usage == ISL_SURF_USAGE_STORAGE_BIT);
+ isl_surf_fill_image_param(&device->isl_dev, image_param_out,
+ &surface->isl, &view);
+ }
+}
+
+static VkImageAspectFlags
+remap_aspect_flags(VkImageAspectFlags view_aspects)
+{
+ if (view_aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) {
+ if (_mesa_bitcount(view_aspects) == 1)
+ return VK_IMAGE_ASPECT_COLOR_BIT;
+
+ VkImageAspectFlags color_aspects = 0;
+ for (uint32_t i = 0; i < _mesa_bitcount(view_aspects); i++)
+ color_aspects |= VK_IMAGE_ASPECT_PLANE_0_BIT_KHR << i;
+ return color_aspects;
+ }
+ /* No special remapping needed for depth & stencil aspects. */
+ return view_aspects;
+}
VkResult
anv_CreateImageView(VkDevice _device,
ANV_FROM_HANDLE(anv_image, image, pCreateInfo->image);
struct anv_image_view *iview;
- iview = vk_alloc2(&device->alloc, pAllocator, sizeof(*iview), 8,
+ iview = vk_zalloc2(&device->alloc, pAllocator, sizeof(*iview), 8,
VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
if (iview == NULL)
return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
assert(range->layerCount > 0);
assert(range->baseMipLevel < image->levels);
- assert(image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
- VK_IMAGE_USAGE_STORAGE_BIT |
- VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT |
- VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT));
+
+ const VkImageViewUsageCreateInfoKHR *usage_info =
+ vk_find_struct_const(pCreateInfo, IMAGE_VIEW_USAGE_CREATE_INFO_KHR);
+ VkImageUsageFlags view_usage = usage_info ? usage_info->usage : image->usage;
+ /* View usage should be a subset of image usage */
+ assert((view_usage & ~image->usage) == 0);
+ assert(view_usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
+ VK_IMAGE_USAGE_STORAGE_BIT |
+ VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT |
+ VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT |
+ VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT));
switch (image->type) {
default:
break;
}
- const struct anv_surface *surface =
- anv_image_get_surface_for_aspect_mask(image, range->aspectMask);
+ /* First expand aspects to the image's ones (for example
+ * VK_IMAGE_ASPECT_COLOR_BIT will be converted to
+ * VK_IMAGE_ASPECT_PLANE_0_BIT_KHR | VK_IMAGE_ASPECT_PLANE_1_BIT_KHR |
+ * VK_IMAGE_ASPECT_PLANE_2_BIT_KHR for an image of format
+ * VK_FORMAT_G8_B8_R8_3PLANE_420_UNORM_KHR.
+ */
+ VkImageAspectFlags expanded_aspects =
+ anv_image_expand_aspects(image, range->aspectMask);
iview->image = image;
- iview->bo = image->bo;
- iview->offset = image->offset + surface->offset;
- iview->aspect_mask = pCreateInfo->subresourceRange.aspectMask;
+ /* Remap the expanded aspects for the image view. For example if only
+ * VK_IMAGE_ASPECT_PLANE_1_BIT_KHR was given in range->aspectMask, we will
+ * convert it to VK_IMAGE_ASPECT_COLOR_BIT since from the point of view of
+ * the image view, it only has a single plane.
+ */
+ iview->aspect_mask = remap_aspect_flags(expanded_aspects);
+ iview->n_planes = anv_image_aspect_get_planes(iview->aspect_mask);
iview->vk_format = pCreateInfo->format;
- struct anv_format format = anv_get_format(&device->info, pCreateInfo->format,
- range->aspectMask, image->tiling);
-
- iview->isl = (struct isl_view) {
- .format = format.isl_format,
- .base_level = range->baseMipLevel,
- .levels = anv_get_levelCount(image, range),
- .base_array_layer = range->baseArrayLayer,
- .array_len = anv_get_layerCount(image, range),
- .swizzle = {
- .r = remap_swizzle(pCreateInfo->components.r,
- VK_COMPONENT_SWIZZLE_R, format.swizzle),
- .g = remap_swizzle(pCreateInfo->components.g,
- VK_COMPONENT_SWIZZLE_G, format.swizzle),
- .b = remap_swizzle(pCreateInfo->components.b,
- VK_COMPONENT_SWIZZLE_B, format.swizzle),
- .a = remap_swizzle(pCreateInfo->components.a,
- VK_COMPONENT_SWIZZLE_A, format.swizzle),
- },
- };
-
iview->extent = (VkExtent3D) {
.width = anv_minify(image->extent.width , range->baseMipLevel),
.height = anv_minify(image->extent.height, range->baseMipLevel),
.depth = anv_minify(image->extent.depth , range->baseMipLevel),
};
- if (pCreateInfo->viewType == VK_IMAGE_VIEW_TYPE_3D) {
- iview->isl.base_array_layer = 0;
- iview->isl.array_len = iview->extent.depth;
- }
-
- if (pCreateInfo->viewType == VK_IMAGE_VIEW_TYPE_CUBE ||
- pCreateInfo->viewType == VK_IMAGE_VIEW_TYPE_CUBE_ARRAY) {
- iview->isl.usage = ISL_SURF_USAGE_CUBE_BIT;
- } else {
- iview->isl.usage = 0;
- }
-
- /* Input attachment surfaces for color are allocated and filled
- * out at BeginRenderPass time because they need compression information.
- * Compression is not yet enabled for depth textures and stencil doesn't
- * allow compression so we can just use the texture surface state from the
- * view.
+ /* Now go through the underlying image selected planes (computed in
+ * expanded_aspects) and map them to planes in the image view.
*/
- if (image->usage & VK_IMAGE_USAGE_SAMPLED_BIT ||
- (image->usage & VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT &&
- !(iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT))) {
- iview->sampler_surface_state = alloc_surface_state(device);
- iview->no_aux_sampler_surface_state = alloc_surface_state(device);
-
- /* Sampling is performed in one of two buffer configurations in anv: with
- * an auxiliary buffer or without it. Sampler states aren't always needed
- * for both configurations, but are currently created unconditionally for
- * simplicity.
- *
- * TODO: Consider allocating each surface state only when necessary.
- */
-
- /* Create a sampler state with the optimal aux_usage for sampling. This
- * may use the aux_buffer.
- */
- const enum isl_aux_usage surf_usage =
- anv_layout_to_aux_usage(&device->info, image, iview->aspect_mask,
- VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL);
-
- /* If this is a HiZ buffer we can sample from with a programmable clear
- * value (SKL+), define the clear value to the optimal constant.
- */
- const float red_clear_color = surf_usage == ISL_AUX_USAGE_HIZ &&
- device->info.gen >= 9 ?
- ANV_HZ_FC_VAL : 0.0f;
-
- struct isl_view view = iview->isl;
- view.usage |= ISL_SURF_USAGE_TEXTURE_BIT;
- isl_surf_fill_state(&device->isl_dev,
- iview->sampler_surface_state.map,
- .surf = &surface->isl,
- .view = &view,
- .clear_color.f32 = { red_clear_color,},
- .aux_surf = &image->aux_surface.isl,
- .aux_usage = surf_usage,
- .mocs = device->default_mocs);
-
- /* Create a sampler state that only uses the main buffer. */
- isl_surf_fill_state(&device->isl_dev,
- iview->no_aux_sampler_surface_state.map,
- .surf = &surface->isl,
- .view = &view,
- .mocs = device->default_mocs);
-
- anv_state_flush(device, iview->sampler_surface_state);
- anv_state_flush(device, iview->no_aux_sampler_surface_state);
- } else {
- iview->sampler_surface_state.alloc_size = 0;
- iview->no_aux_sampler_surface_state.alloc_size = 0;
- }
-
- /* NOTE: This one needs to go last since it may stomp isl_view.format */
- if (image->usage & VK_IMAGE_USAGE_STORAGE_BIT) {
- iview->storage_surface_state = alloc_surface_state(device);
- iview->writeonly_storage_surface_state = alloc_surface_state(device);
-
- struct isl_view view = iview->isl;
- view.usage |= ISL_SURF_USAGE_STORAGE_BIT;
-
- /* Write-only accesses always used a typed write instruction and should
- * therefore use the real format.
- */
- isl_surf_fill_state(&device->isl_dev,
- iview->writeonly_storage_surface_state.map,
- .surf = &surface->isl,
- .view = &view,
- .aux_surf = &image->aux_surface.isl,
- .aux_usage = image->aux_usage,
- .mocs = device->default_mocs);
+ uint32_t iaspect_bit, vplane = 0;
+ anv_foreach_image_aspect_bit(iaspect_bit, image, expanded_aspects) {
+ uint32_t iplane =
+ anv_image_aspect_to_plane(expanded_aspects, 1UL << iaspect_bit);
+ VkImageAspectFlags vplane_aspect =
+ anv_plane_to_aspect(iview->aspect_mask, vplane);
+ struct anv_format_plane format =
+ anv_get_format_plane(&device->info, pCreateInfo->format,
+ vplane_aspect, image->tiling);
+
+ iview->planes[vplane].image_plane = iplane;
+
+ iview->planes[vplane].isl = (struct isl_view) {
+ .format = format.isl_format,
+ .base_level = range->baseMipLevel,
+ .levels = anv_get_levelCount(image, range),
+ .base_array_layer = range->baseArrayLayer,
+ .array_len = anv_get_layerCount(image, range),
+ .swizzle = {
+ .r = remap_swizzle(pCreateInfo->components.r,
+ VK_COMPONENT_SWIZZLE_R, format.swizzle),
+ .g = remap_swizzle(pCreateInfo->components.g,
+ VK_COMPONENT_SWIZZLE_G, format.swizzle),
+ .b = remap_swizzle(pCreateInfo->components.b,
+ VK_COMPONENT_SWIZZLE_B, format.swizzle),
+ .a = remap_swizzle(pCreateInfo->components.a,
+ VK_COMPONENT_SWIZZLE_A, format.swizzle),
+ },
+ };
+
+ if (pCreateInfo->viewType == VK_IMAGE_VIEW_TYPE_3D) {
+ iview->planes[vplane].isl.base_array_layer = 0;
+ iview->planes[vplane].isl.array_len = iview->extent.depth;
+ }
- if (isl_has_matching_typed_storage_image_format(&device->info,
- format.isl_format)) {
- /* Typed surface reads support a very limited subset of the shader
- * image formats. Translate it into the closest format the hardware
- * supports.
- */
- view.format = isl_lower_storage_image_format(&device->info,
- format.isl_format);
-
- isl_surf_fill_state(&device->isl_dev,
- iview->storage_surface_state.map,
- .surf = &surface->isl,
- .view = &view,
- .aux_surf = &image->aux_surface.isl,
- .aux_usage = image->aux_usage,
- .mocs = device->default_mocs);
+ if (pCreateInfo->viewType == VK_IMAGE_VIEW_TYPE_CUBE ||
+ pCreateInfo->viewType == VK_IMAGE_VIEW_TYPE_CUBE_ARRAY) {
+ iview->planes[vplane].isl.usage = ISL_SURF_USAGE_CUBE_BIT;
} else {
- anv_fill_buffer_surface_state(device, iview->storage_surface_state,
- ISL_FORMAT_RAW,
- iview->offset,
- iview->bo->size - iview->offset, 1);
+ iview->planes[vplane].isl.usage = 0;
}
- isl_surf_fill_image_param(&device->isl_dev,
- &iview->storage_image_param,
- &surface->isl, &iview->isl);
+ if (view_usage & VK_IMAGE_USAGE_SAMPLED_BIT ||
+ (view_usage & VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT &&
+ !(iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT))) {
+ iview->planes[vplane].optimal_sampler_surface_state.state = alloc_surface_state(device);
+ iview->planes[vplane].general_sampler_surface_state.state = alloc_surface_state(device);
+
+ enum isl_aux_usage general_aux_usage =
+ anv_layout_to_aux_usage(&device->info, image, 1UL << iaspect_bit,
+ VK_IMAGE_LAYOUT_GENERAL);
+ enum isl_aux_usage optimal_aux_usage =
+ anv_layout_to_aux_usage(&device->info, image, 1UL << iaspect_bit,
+ VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL);
+
+ anv_image_fill_surface_state(device, image, 1ULL << iaspect_bit,
+ &iview->planes[vplane].isl,
+ ISL_SURF_USAGE_TEXTURE_BIT,
+ optimal_aux_usage, NULL,
+ ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL,
+ &iview->planes[vplane].optimal_sampler_surface_state,
+ NULL);
+
+ anv_image_fill_surface_state(device, image, 1ULL << iaspect_bit,
+ &iview->planes[vplane].isl,
+ ISL_SURF_USAGE_TEXTURE_BIT,
+ general_aux_usage, NULL,
+ 0,
+ &iview->planes[vplane].general_sampler_surface_state,
+ NULL);
+ }
- anv_state_flush(device, iview->storage_surface_state);
- anv_state_flush(device, iview->writeonly_storage_surface_state);
- } else {
- iview->storage_surface_state.alloc_size = 0;
- iview->writeonly_storage_surface_state.alloc_size = 0;
+ /* NOTE: This one needs to go last since it may stomp isl_view.format */
+ if (view_usage & VK_IMAGE_USAGE_STORAGE_BIT) {
+ iview->planes[vplane].storage_surface_state.state = alloc_surface_state(device);
+ iview->planes[vplane].writeonly_storage_surface_state.state = alloc_surface_state(device);
+
+ anv_image_fill_surface_state(device, image, 1ULL << iaspect_bit,
+ &iview->planes[vplane].isl,
+ ISL_SURF_USAGE_STORAGE_BIT,
+ ISL_AUX_USAGE_NONE, NULL,
+ 0,
+ &iview->planes[vplane].storage_surface_state,
+ &iview->planes[vplane].storage_image_param);
+
+ anv_image_fill_surface_state(device, image, 1ULL << iaspect_bit,
+ &iview->planes[vplane].isl,
+ ISL_SURF_USAGE_STORAGE_BIT,
+ ISL_AUX_USAGE_NONE, NULL,
+ ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY,
+ &iview->planes[vplane].writeonly_storage_surface_state,
+ NULL);
+ }
+
+ vplane++;
}
*pView = anv_image_view_to_handle(iview);
if (!iview)
return;
- if (iview->sampler_surface_state.alloc_size > 0) {
- anv_state_pool_free(&device->surface_state_pool,
- iview->sampler_surface_state);
- }
+ for (uint32_t plane = 0; plane < iview->n_planes; plane++) {
+ if (iview->planes[plane].optimal_sampler_surface_state.state.alloc_size > 0) {
+ anv_state_pool_free(&device->surface_state_pool,
+ iview->planes[plane].optimal_sampler_surface_state.state);
+ }
- if (iview->storage_surface_state.alloc_size > 0) {
- anv_state_pool_free(&device->surface_state_pool,
- iview->storage_surface_state);
- }
+ if (iview->planes[plane].general_sampler_surface_state.state.alloc_size > 0) {
+ anv_state_pool_free(&device->surface_state_pool,
+ iview->planes[plane].general_sampler_surface_state.state);
+ }
- if (iview->writeonly_storage_surface_state.alloc_size > 0) {
- anv_state_pool_free(&device->surface_state_pool,
- iview->writeonly_storage_surface_state);
+ if (iview->planes[plane].storage_surface_state.state.alloc_size > 0) {
+ anv_state_pool_free(&device->surface_state_pool,
+ iview->planes[plane].storage_surface_state.state);
+ }
+
+ if (iview->planes[plane].writeonly_storage_surface_state.state.alloc_size > 0) {
+ anv_state_pool_free(&device->surface_state_pool,
+ iview->planes[plane].writeonly_storage_surface_state.state);
+ }
}
vk_free2(&device->alloc, pAllocator, iview);
anv_image_get_surface_for_aspect_mask(const struct anv_image *image,
VkImageAspectFlags aspect_mask)
{
+ VkImageAspectFlags sanitized_mask;
+
switch (aspect_mask) {
case VK_IMAGE_ASPECT_COLOR_BIT:
assert(image->aspects == VK_IMAGE_ASPECT_COLOR_BIT);
- return &image->color_surface;
+ sanitized_mask = VK_IMAGE_ASPECT_COLOR_BIT;
+ break;
case VK_IMAGE_ASPECT_DEPTH_BIT:
assert(image->aspects & VK_IMAGE_ASPECT_DEPTH_BIT);
- return &image->depth_surface;
+ sanitized_mask = VK_IMAGE_ASPECT_DEPTH_BIT;
+ break;
case VK_IMAGE_ASPECT_STENCIL_BIT:
assert(image->aspects & VK_IMAGE_ASPECT_STENCIL_BIT);
- return &image->stencil_surface;
+ sanitized_mask = VK_IMAGE_ASPECT_STENCIL_BIT;
+ break;
case VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT:
/* FINISHME: The Vulkan spec (git a511ba2) requires support for
* combined depth stencil formats. Specifically, it states:
* stencil surfaces from the underlying surface.
*/
if (image->aspects & VK_IMAGE_ASPECT_DEPTH_BIT) {
- return &image->depth_surface;
+ sanitized_mask = VK_IMAGE_ASPECT_DEPTH_BIT;
} else {
assert(image->aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
- return &image->stencil_surface;
+ sanitized_mask = VK_IMAGE_ASPECT_STENCIL_BIT;
}
- default:
+ break;
+ case VK_IMAGE_ASPECT_PLANE_0_BIT_KHR:
+ assert((image->aspects & ~VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) == 0);
+ sanitized_mask = VK_IMAGE_ASPECT_PLANE_0_BIT_KHR;
+ break;
+ case VK_IMAGE_ASPECT_PLANE_1_BIT_KHR:
+ assert((image->aspects & ~VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) == 0);
+ sanitized_mask = VK_IMAGE_ASPECT_PLANE_1_BIT_KHR;
+ break;
+ case VK_IMAGE_ASPECT_PLANE_2_BIT_KHR:
+ assert((image->aspects & ~VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) == 0);
+ sanitized_mask = VK_IMAGE_ASPECT_PLANE_2_BIT_KHR;
+ break;
+ default:
unreachable("image does not have aspect");
return NULL;
}
+
+ uint32_t plane = anv_image_aspect_to_plane(image->aspects, sanitized_mask);
+ return &image->planes[plane].surface;
}
projects / mesa.git / blobdiff