#include <unistd.h>
#include <fcntl.h>
#include <sys/mman.h>
+#include "drm-uapi/drm_fourcc.h"
#include "anv_private.h"
#include "util/debug.h"
+#include "vk_util.h"
+#include "util/u_math.h"
+
+#include "common/gen_aux_map.h"
#include "vk_format_info.h"
-/**
- * Exactly one bit must be set in \a aspect.
- */
static isl_surf_usage_flags_t
-choose_isl_surf_usage(VkImageUsageFlags vk_usage,
- VkImageAspectFlags aspect)
+choose_isl_surf_usage(VkImageCreateFlags vk_create_flags,
+ VkImageUsageFlags vk_usage,
+ isl_surf_usage_flags_t isl_extra_usage,
+ VkImageAspectFlagBits aspect)
{
- isl_surf_usage_flags_t isl_usage = 0;
+ isl_surf_usage_flags_t isl_usage = isl_extra_usage;
if (vk_usage & VK_IMAGE_USAGE_SAMPLED_BIT)
isl_usage |= ISL_SURF_USAGE_TEXTURE_BIT;
if (vk_usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT)
isl_usage |= ISL_SURF_USAGE_RENDER_TARGET_BIT;
- if (vk_usage & VK_IMAGE_CREATE_CUBE_COMPATIBLE_BIT)
+ if (vk_create_flags & VK_IMAGE_CREATE_CUBE_COMPATIBLE_BIT)
isl_usage |= ISL_SURF_USAGE_CUBE_BIT;
/* Even if we're only using it for transfer operations, clears to depth and
isl_usage |= ISL_SURF_USAGE_STENCIL_BIT;
break;
case VK_IMAGE_ASPECT_COLOR_BIT:
+ case VK_IMAGE_ASPECT_PLANE_0_BIT:
+ case VK_IMAGE_ASPECT_PLANE_1_BIT:
+ case VK_IMAGE_ASPECT_PLANE_2_BIT:
break;
default:
unreachable("bad VkImageAspect");
return isl_usage;
}
-/**
- * Exactly one bit must be set in \a aspect.
- */
-static struct anv_surface *
-get_surface(struct anv_image *image, VkImageAspectFlags aspect)
+static isl_tiling_flags_t
+choose_isl_tiling_flags(const struct anv_image_create_info *anv_info,
+ const struct isl_drm_modifier_info *isl_mod_info,
+ bool legacy_scanout)
{
- switch (aspect) {
+ const VkImageCreateInfo *base_info = anv_info->vk_info;
+ isl_tiling_flags_t flags = 0;
+
+ switch (base_info->tiling) {
default:
- unreachable("bad VkImageAspect");
- case VK_IMAGE_ASPECT_COLOR_BIT:
- return &image->color_surface;
- case VK_IMAGE_ASPECT_DEPTH_BIT:
- return &image->depth_surface;
- case VK_IMAGE_ASPECT_STENCIL_BIT:
- return &image->stencil_surface;
+ unreachable("bad VkImageTiling");
+ case VK_IMAGE_TILING_OPTIMAL:
+ flags = ISL_TILING_ANY_MASK;
+ break;
+ case VK_IMAGE_TILING_LINEAR:
+ flags = ISL_TILING_LINEAR_BIT;
+ break;
+ }
+
+ if (anv_info->isl_tiling_flags)
+ flags &= anv_info->isl_tiling_flags;
+
+ if (legacy_scanout)
+ flags &= ISL_TILING_LINEAR_BIT | ISL_TILING_X_BIT;
+
+ if (isl_mod_info)
+ flags &= 1 << isl_mod_info->tiling;
+
+ assert(flags);
+
+ return flags;
+}
+
+static struct anv_surface *
+get_surface(struct anv_image *image, VkImageAspectFlagBits aspect)
+{
+ uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
+ return &image->planes[plane].surface;
+}
+
+static void
+add_surface(struct anv_image *image, struct anv_surface *surf, uint32_t plane)
+{
+ assert(surf->isl.size_B > 0); /* isl surface must be initialized */
+
+ if (image->disjoint) {
+ surf->offset = align_u32(image->planes[plane].size,
+ surf->isl.alignment_B);
+ /* Plane offset is always 0 when it's disjoint. */
+ } else {
+ surf->offset = align_u32(image->size, surf->isl.alignment_B);
+ /* Determine plane's offset only once when the first surface is added. */
+ if (image->planes[plane].size == 0)
+ image->planes[plane].offset = image->size;
}
+
+ image->size = surf->offset + surf->isl.size_B;
+ image->planes[plane].size = (surf->offset + surf->isl.size_B) - image->planes[plane].offset;
+
+ image->alignment = MAX2(image->alignment, surf->isl.alignment_B);
+ image->planes[plane].alignment = MAX2(image->planes[plane].alignment,
+ surf->isl.alignment_B);
}
+
+static bool
+all_formats_ccs_e_compatible(const struct gen_device_info *devinfo,
+ const VkImageFormatListCreateInfoKHR *fmt_list,
+ struct anv_image *image)
+{
+ enum isl_format format =
+ anv_get_isl_format(devinfo, image->vk_format,
+ VK_IMAGE_ASPECT_COLOR_BIT, image->tiling);
+
+ if (!isl_format_supports_ccs_e(devinfo, format))
+ return false;
+
+ if (!(image->create_flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT))
+ return true;
+
+ if (!fmt_list || fmt_list->viewFormatCount == 0)
+ return false;
+
+ for (uint32_t i = 0; i < fmt_list->viewFormatCount; i++) {
+ enum isl_format view_format =
+ anv_get_isl_format(devinfo, fmt_list->pViewFormats[i],
+ VK_IMAGE_ASPECT_COLOR_BIT, image->tiling);
+
+ if (!isl_formats_are_ccs_e_compatible(devinfo, format, view_format))
+ return false;
+ }
+
+ return true;
+}
+
+/**
+ * For color images that have an auxiliary surface, request allocation for an
+ * additional buffer that mainly stores fast-clear values. Use of this buffer
+ * allows us to access the image's subresources while being aware of their
+ * fast-clear values in non-trivial cases (e.g., outside of a render pass in
+ * which a fast clear has occurred).
+ *
+ * In order to avoid having multiple clear colors for a single plane of an
+ * image (hence a single RENDER_SURFACE_STATE), we only allow fast-clears on
+ * the first slice (level 0, layer 0). At the time of our testing (Jan 17,
+ * 2018), there were no known applications which would benefit from fast-
+ * clearing more than just the first slice.
+ *
+ * The fast clear portion of the image is laid out in the following order:
+ *
+ * * 1 or 4 dwords (depending on hardware generation) for the clear color
+ * * 1 dword for the anv_fast_clear_type of the clear color
+ * * On gen9+, 1 dword per level and layer of the image (3D levels count
+ * multiple layers) in level-major order for compression state.
+ *
+ * For the purpose of discoverability, the algorithm used to manage
+ * compression and fast-clears is described here:
+ *
+ * * On a transition from UNDEFINED or PREINITIALIZED to a defined layout,
+ * all of the values in the fast clear portion of the image are initialized
+ * to default values.
+ *
+ * * On fast-clear, the clear value is written into surface state and also
+ * into the buffer and the fast clear type is set appropriately. Both
+ * setting the fast-clear value in the buffer and setting the fast-clear
+ * type happen from the GPU using MI commands.
+ *
+ * * Whenever a render or blorp operation is performed with CCS_E, we call
+ * genX(cmd_buffer_mark_image_written) to set the compression state to
+ * true (which is represented by UINT32_MAX).
+ *
+ * * On pipeline barrier transitions, the worst-case transition is computed
+ * from the image layouts. The command streamer inspects the fast clear
+ * type and compression state dwords and constructs a predicate. The
+ * worst-case resolve is performed with the given predicate and the fast
+ * clear and compression state is set accordingly.
+ *
+ * See anv_layout_to_aux_usage and anv_layout_to_fast_clear_type functions for
+ * details on exactly what is allowed in what layouts.
+ *
+ * On gen7-9, we do not have a concept of indirect clear colors in hardware.
+ * In order to deal with this, we have to do some clear color management.
+ *
+ * * For LOAD_OP_LOAD at the top of a renderpass, we have to copy the clear
+ * value from the buffer into the surface state with MI commands.
+ *
+ * * For any blorp operations, we pass the address to the clear value into
+ * blorp and it knows to copy the clear color.
+ */
static void
-add_surface(struct anv_image *image, struct anv_surface *surf)
+add_aux_state_tracking_buffer(struct anv_image *image,
+ uint32_t plane,
+ const struct anv_device *device)
{
- assert(surf->isl.size > 0); /* isl surface must be initialized */
+ assert(image && device);
+ assert(image->planes[plane].aux_surface.isl.size_B > 0 &&
+ image->aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV);
+
+ /* Compressed images must be tiled and therefore everything should be 4K
+ * aligned. The CCS has the same alignment requirements. This is good
+ * because we need at least dword-alignment for MI_LOAD/STORE operations.
+ */
+ assert(image->alignment % 4 == 0);
+ assert((image->planes[plane].offset + image->planes[plane].size) % 4 == 0);
+
+ /* This buffer should be at the very end of the plane. */
+ if (image->disjoint) {
+ assert(image->planes[plane].size ==
+ (image->planes[plane].offset + image->planes[plane].size));
+ } else {
+ assert(image->size ==
+ (image->planes[plane].offset + image->planes[plane].size));
+ }
- surf->offset = align_u32(image->size, surf->isl.alignment);
- image->size = surf->offset + surf->isl.size;
- image->alignment = MAX2(image->alignment, surf->isl.alignment);
+ const unsigned clear_color_state_size = device->info.gen >= 10 ?
+ device->isl_dev.ss.clear_color_state_size :
+ device->isl_dev.ss.clear_value_size;
+
+ /* Clear color and fast clear type */
+ unsigned state_size = clear_color_state_size + 4;
+
+ /* We only need to track compression on CCS_E surfaces. */
+ if (image->planes[plane].aux_usage == ISL_AUX_USAGE_CCS_E) {
+ if (image->type == VK_IMAGE_TYPE_3D) {
+ for (uint32_t l = 0; l < image->levels; l++)
+ state_size += anv_minify(image->extent.depth, l) * 4;
+ } else {
+ state_size += image->levels * image->array_size * 4;
+ }
+ }
+
+ /* Add some padding to make sure the fast clear color state buffer starts at
+ * a 4K alignment. We believe that 256B might be enough, but due to lack of
+ * testing we will leave this as 4K for now.
+ */
+ image->planes[plane].size = ALIGN(image->planes[plane].size, 4096);
+ image->size = ALIGN(image->size, 4096);
+
+ assert(image->planes[plane].offset % 4096 == 0);
+
+ image->planes[plane].fast_clear_state_offset =
+ image->planes[plane].offset + image->planes[plane].size;
+
+ image->planes[plane].size += state_size;
+ image->size += state_size;
}
/**
* Initialize the anv_image::*_surface selected by \a aspect. Then update the
* image's memory requirements (that is, the image's size and alignment).
- *
- * Exactly one bit must be set in \a aspect.
*/
static VkResult
make_surface(const struct anv_device *dev,
struct anv_image *image,
- const struct anv_image_create_info *anv_info,
- VkImageAspectFlags aspect)
+ uint32_t stride,
+ isl_tiling_flags_t tiling_flags,
+ isl_surf_usage_flags_t isl_extra_usage_flags,
+ VkImageAspectFlagBits aspect)
{
- const VkImageCreateInfo *vk_info = anv_info->vk_info;
- bool ok UNUSED;
+ bool ok;
static const enum isl_surf_dim vk_to_isl_surf_dim[] = {
[VK_IMAGE_TYPE_1D] = ISL_SURF_DIM_1D,
[VK_IMAGE_TYPE_3D] = ISL_SURF_DIM_3D,
};
- /* Translate the Vulkan tiling to an equivalent ISL tiling, then filter the
- * result with an optionally provided ISL tiling argument.
- */
- isl_tiling_flags_t tiling_flags =
- (vk_info->tiling == VK_IMAGE_TILING_LINEAR) ?
- ISL_TILING_LINEAR_BIT : ISL_TILING_ANY_MASK;
-
- if (anv_info->isl_tiling_flags)
- tiling_flags &= anv_info->isl_tiling_flags;
+ image->extent = anv_sanitize_image_extent(image->type, image->extent);
- assert(tiling_flags);
+ const unsigned plane = anv_image_aspect_to_plane(image->aspects, aspect);
+ const struct anv_format_plane plane_format =
+ anv_get_format_plane(&dev->info, image->vk_format, aspect, image->tiling);
+ struct anv_surface *anv_surf = &image->planes[plane].surface;
- struct anv_surface *anv_surf = get_surface(image, aspect);
+ const isl_surf_usage_flags_t usage =
+ choose_isl_surf_usage(image->create_flags, image->usage,
+ isl_extra_usage_flags, aspect);
- image->extent = anv_sanitize_image_extent(vk_info->imageType,
- vk_info->extent);
+ /* If an image is created as BLOCK_TEXEL_VIEW_COMPATIBLE, then we need to
+ * fall back to linear on Broadwell and earlier because we aren't
+ * guaranteed that we can handle offsets correctly. On Sky Lake, the
+ * horizontal and vertical alignments are sufficiently high that we can
+ * just use RENDER_SURFACE_STATE::X/Y Offset.
+ */
+ bool needs_shadow = false;
+ isl_surf_usage_flags_t shadow_usage = 0;
+ if (dev->info.gen <= 8 &&
+ (image->create_flags & VK_IMAGE_CREATE_BLOCK_TEXEL_VIEW_COMPATIBLE_BIT) &&
+ image->tiling == VK_IMAGE_TILING_OPTIMAL) {
+ assert(isl_format_is_compressed(plane_format.isl_format));
+ tiling_flags = ISL_TILING_LINEAR_BIT;
+ needs_shadow = true;
+ shadow_usage = ISL_SURF_USAGE_TEXTURE_BIT |
+ (usage & ISL_SURF_USAGE_CUBE_BIT);
+ }
- enum isl_format format = anv_get_isl_format(&dev->info, vk_info->format,
- aspect, vk_info->tiling);
- assert(format != ISL_FORMAT_UNSUPPORTED);
+ if (dev->info.gen <= 7 &&
+ aspect == VK_IMAGE_ASPECT_STENCIL_BIT &&
+ (image->stencil_usage & VK_IMAGE_USAGE_SAMPLED_BIT)) {
+ needs_shadow = true;
+ shadow_usage = ISL_SURF_USAGE_TEXTURE_BIT |
+ (usage & ISL_SURF_USAGE_CUBE_BIT);
+ }
ok = isl_surf_init(&dev->isl_dev, &anv_surf->isl,
- .dim = vk_to_isl_surf_dim[vk_info->imageType],
- .format = format,
- .width = image->extent.width,
- .height = image->extent.height,
+ .dim = vk_to_isl_surf_dim[image->type],
+ .format = plane_format.isl_format,
+ .width = image->extent.width / plane_format.denominator_scales[0],
+ .height = image->extent.height / plane_format.denominator_scales[1],
.depth = image->extent.depth,
- .levels = vk_info->mipLevels,
- .array_len = vk_info->arrayLayers,
- .samples = vk_info->samples,
- .min_alignment = 0,
- .row_pitch = anv_info->stride,
- .usage = choose_isl_surf_usage(image->usage, aspect),
+ .levels = image->levels,
+ .array_len = image->array_size,
+ .samples = image->samples,
+ .min_alignment_B = 0,
+ .row_pitch_B = stride,
+ .usage = usage,
.tiling_flags = tiling_flags);
- /* isl_surf_init() will fail only if provided invalid input. Invalid input
- * is illegal in Vulkan.
+ if (!ok)
+ return VK_ERROR_OUT_OF_DEVICE_MEMORY;
+
+ image->planes[plane].aux_usage = ISL_AUX_USAGE_NONE;
+
+ add_surface(image, anv_surf, plane);
+
+ /* If an image is created as BLOCK_TEXEL_VIEW_COMPATIBLE, then we need to
+ * create an identical tiled shadow surface for use while texturing so we
+ * don't get garbage performance. If we're on gen7 and the image contains
+ * stencil, then we need to maintain a shadow because we can't texture from
+ * W-tiled images.
*/
- assert(ok);
+ if (needs_shadow) {
+ ok = isl_surf_init(&dev->isl_dev, &image->planes[plane].shadow_surface.isl,
+ .dim = vk_to_isl_surf_dim[image->type],
+ .format = plane_format.isl_format,
+ .width = image->extent.width,
+ .height = image->extent.height,
+ .depth = image->extent.depth,
+ .levels = image->levels,
+ .array_len = image->array_size,
+ .samples = image->samples,
+ .min_alignment_B = 0,
+ .row_pitch_B = stride,
+ .usage = shadow_usage,
+ .tiling_flags = ISL_TILING_ANY_MASK);
+
+ /* isl_surf_init() will fail only if provided invalid input. Invalid input
+ * is illegal in Vulkan.
+ */
+ assert(ok);
- add_surface(image, anv_surf);
+ add_surface(image, &image->planes[plane].shadow_surface, plane);
+ }
/* Add a HiZ surface to a depth buffer that will be used for rendering.
*/
if (!(image->usage & VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT)) {
/* It will never be used as an attachment, HiZ is pointless. */
} else if (dev->info.gen == 7) {
- anv_perf_warn("Implement gen7 HiZ");
- } else if (vk_info->mipLevels > 1) {
- anv_perf_warn("Enable multi-LOD HiZ");
- } else if (vk_info->arrayLayers > 1) {
- anv_perf_warn("Implement multi-arrayLayer HiZ clears and resolves");
- } else if (dev->info.gen == 8 && vk_info->samples > 1) {
- anv_perf_warn("Enable gen8 multisampled HiZ");
+ anv_perf_warn(dev->instance, image, "Implement gen7 HiZ");
+ } else if (image->levels > 1) {
+ anv_perf_warn(dev->instance, image, "Enable multi-LOD HiZ");
+ } else if (image->array_size > 1) {
+ anv_perf_warn(dev->instance, image,
+ "Implement multi-arrayLayer HiZ clears and resolves");
+ } else if (dev->info.gen == 8 && image->samples > 1) {
+ anv_perf_warn(dev->instance, image, "Enable gen8 multisampled HiZ");
} else if (!unlikely(INTEL_DEBUG & DEBUG_NO_HIZ)) {
- assert(image->aux_surface.isl.size == 0);
- ok = isl_surf_get_hiz_surf(&dev->isl_dev, &image->depth_surface.isl,
- &image->aux_surface.isl);
+ assert(image->planes[plane].aux_surface.isl.size_B == 0);
+ ok = isl_surf_get_hiz_surf(&dev->isl_dev,
+ &image->planes[plane].surface.isl,
+ &image->planes[plane].aux_surface.isl);
assert(ok);
- add_surface(image, &image->aux_surface);
- image->aux_usage = ISL_AUX_USAGE_HIZ;
+ add_surface(image, &image->planes[plane].aux_surface, plane);
+ image->planes[plane].aux_usage = ISL_AUX_USAGE_HIZ;
}
- } else if (aspect == VK_IMAGE_ASPECT_COLOR_BIT && vk_info->samples == 1) {
- if (!unlikely(INTEL_DEBUG & DEBUG_NO_RBC)) {
- assert(image->aux_surface.isl.size == 0);
- ok = isl_surf_get_ccs_surf(&dev->isl_dev, &anv_surf->isl,
- &image->aux_surface.isl);
+ } else if ((aspect & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) && image->samples == 1) {
+ /* TODO: Disallow compression with :
+ *
+ * 1) non multiplanar images (We appear to hit a sampler bug with
+ * CCS & R16G16 format. Putting the clear state a page/4096bytes
+ * further fixes the issue).
+ *
+ * 2) alias images, because they might be aliases of images
+ * described in 1)
+ *
+ * 3) compression disabled by debug
+ */
+ const bool allow_compression =
+ image->n_planes == 1 &&
+ (image->create_flags & VK_IMAGE_CREATE_ALIAS_BIT) == 0 &&
+ likely((INTEL_DEBUG & DEBUG_NO_RBC) == 0);
+
+ if (allow_compression) {
+ assert(image->planes[plane].aux_surface.isl.size_B == 0);
+ ok = isl_surf_get_ccs_surf(&dev->isl_dev,
+ &image->planes[plane].surface.isl,
+ &image->planes[plane].aux_surface.isl,
+ NULL, 0);
if (ok) {
- add_surface(image, &image->aux_surface);
+
+ /* Disable CCS when it is not useful (i.e., when you can't render
+ * to the image with CCS enabled).
+ */
+ if (!isl_format_supports_rendering(&dev->info,
+ plane_format.isl_format)) {
+ /* While it may be technically possible to enable CCS for this
+ * image, we currently don't have things hooked up to get it
+ * working.
+ */
+ anv_perf_warn(dev->instance, image,
+ "This image format doesn't support rendering. "
+ "Not allocating an CCS buffer.");
+ image->planes[plane].aux_surface.isl.size_B = 0;
+ return VK_SUCCESS;
+ }
/* For images created without MUTABLE_FORMAT_BIT set, we know that
* they will always be used with the original format. In
* a render target. This means that it's safe to just leave
* compression on at all times for these formats.
*/
- if (!(vk_info->usage & VK_IMAGE_USAGE_STORAGE_BIT) &&
- !(vk_info->flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT) &&
- isl_format_supports_ccs_e(&dev->info, format)) {
- image->aux_usage = ISL_AUX_USAGE_CCS_E;
+ if (!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT) &&
+ image->ccs_e_compatible) {
+ image->planes[plane].aux_usage = ISL_AUX_USAGE_CCS_E;
+ } else if (dev->info.gen >= 12) {
+ anv_perf_warn(dev->instance, image,
+ "The CCS_D aux mode is not yet handled on "
+ "Gen12+. Not allocating a CCS buffer.");
+ image->planes[plane].aux_surface.isl.size_B = 0;
+ return VK_SUCCESS;
}
+
+ add_surface(image, &image->planes[plane].aux_surface, plane);
+ add_aux_state_tracking_buffer(image, plane, dev);
}
}
- } else if (aspect == VK_IMAGE_ASPECT_COLOR_BIT && vk_info->samples > 1) {
- assert(image->aux_surface.isl.size == 0);
- assert(!(vk_info->usage & VK_IMAGE_USAGE_STORAGE_BIT));
- ok = isl_surf_get_mcs_surf(&dev->isl_dev, &anv_surf->isl,
- &image->aux_surface.isl);
+ } else if ((aspect & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) && image->samples > 1) {
+ assert(!(image->usage & VK_IMAGE_USAGE_STORAGE_BIT));
+ assert(image->planes[plane].aux_surface.isl.size_B == 0);
+ ok = isl_surf_get_mcs_surf(&dev->isl_dev,
+ &image->planes[plane].surface.isl,
+ &image->planes[plane].aux_surface.isl);
if (ok) {
- add_surface(image, &image->aux_surface);
- image->aux_usage = ISL_AUX_USAGE_MCS;
+ add_surface(image, &image->planes[plane].aux_surface, plane);
+ add_aux_state_tracking_buffer(image, plane, dev);
+ image->planes[plane].aux_usage = ISL_AUX_USAGE_MCS;
}
}
+ assert((image->planes[plane].offset + image->planes[plane].size) == image->size);
+
+ /* Upper bound of the last surface should be smaller than the plane's
+ * size.
+ */
+ assert((MAX2(image->planes[plane].surface.offset,
+ image->planes[plane].aux_surface.offset) +
+ (image->planes[plane].aux_surface.isl.size_B > 0 ?
+ image->planes[plane].aux_surface.isl.size_B :
+ image->planes[plane].surface.isl.size_B)) <=
+ (image->planes[plane].offset + image->planes[plane].size));
+
+ if (image->planes[plane].aux_surface.isl.size_B) {
+ /* assert(image->planes[plane].fast_clear_state_offset == */
+ /* (image->planes[plane].aux_surface.offset + image->planes[plane].aux_surface.isl.size_B)); */
+ assert(image->planes[plane].fast_clear_state_offset <
+ (image->planes[plane].offset + image->planes[plane].size));
+ }
+
return VK_SUCCESS;
}
+static uint32_t
+score_drm_format_mod(uint64_t modifier)
+{
+ switch (modifier) {
+ case DRM_FORMAT_MOD_LINEAR: return 1;
+ case I915_FORMAT_MOD_X_TILED: return 2;
+ case I915_FORMAT_MOD_Y_TILED: return 3;
+ case I915_FORMAT_MOD_Y_TILED_CCS: return 4;
+ default: unreachable("bad DRM format modifier");
+ }
+}
+
+static const struct isl_drm_modifier_info *
+choose_drm_format_mod(const struct anv_physical_device *device,
+ uint32_t modifier_count, const uint64_t *modifiers)
+{
+ uint64_t best_mod = UINT64_MAX;
+ uint32_t best_score = 0;
+
+ for (uint32_t i = 0; i < modifier_count; ++i) {
+ uint32_t score = score_drm_format_mod(modifiers[i]);
+ if (score > best_score) {
+ best_mod = modifiers[i];
+ best_score = score;
+ }
+ }
+
+ if (best_score > 0)
+ return isl_drm_modifier_get_info(best_mod);
+ else
+ return NULL;
+}
+
VkResult
anv_image_create(VkDevice _device,
const struct anv_image_create_info *create_info,
{
ANV_FROM_HANDLE(anv_device, device, _device);
const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
+ const struct isl_drm_modifier_info *isl_mod_info = NULL;
struct anv_image *image = NULL;
VkResult r;
assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO);
+ const struct wsi_image_create_info *wsi_info =
+ vk_find_struct_const(pCreateInfo->pNext, WSI_IMAGE_CREATE_INFO_MESA);
+ if (wsi_info && wsi_info->modifier_count > 0) {
+ isl_mod_info = choose_drm_format_mod(&device->instance->physicalDevice,
+ wsi_info->modifier_count,
+ wsi_info->modifiers);
+ assert(isl_mod_info);
+ }
+
anv_assert(pCreateInfo->mipLevels > 0);
anv_assert(pCreateInfo->arrayLayers > 0);
anv_assert(pCreateInfo->samples > 0);
anv_assert(pCreateInfo->extent.height > 0);
anv_assert(pCreateInfo->extent.depth > 0);
- image = vk_alloc2(&device->alloc, alloc, sizeof(*image), 8,
- VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
+ image = vk_zalloc2(&device->alloc, alloc, sizeof(*image), 8,
+ VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
if (!image)
return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
- memset(image, 0, sizeof(*image));
image->type = pCreateInfo->imageType;
image->extent = pCreateInfo->extent;
image->vk_format = pCreateInfo->format;
+ image->format = anv_get_format(pCreateInfo->format);
image->aspects = vk_format_aspects(image->vk_format);
image->levels = pCreateInfo->mipLevels;
image->array_size = pCreateInfo->arrayLayers;
image->samples = pCreateInfo->samples;
image->usage = pCreateInfo->usage;
+ image->create_flags = pCreateInfo->flags;
image->tiling = pCreateInfo->tiling;
- image->aux_usage = ISL_AUX_USAGE_NONE;
+ image->disjoint = pCreateInfo->flags & VK_IMAGE_CREATE_DISJOINT_BIT;
+ image->needs_set_tiling = wsi_info && wsi_info->scanout;
+ image->drm_format_mod = isl_mod_info ? isl_mod_info->modifier :
+ DRM_FORMAT_MOD_INVALID;
+
+ if (image->aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
+ image->stencil_usage = pCreateInfo->usage;
+ const VkImageStencilUsageCreateInfoEXT *stencil_usage_info =
+ vk_find_struct_const(pCreateInfo->pNext,
+ IMAGE_STENCIL_USAGE_CREATE_INFO_EXT);
+ if (stencil_usage_info)
+ image->stencil_usage = stencil_usage_info->stencilUsage;
+ }
+
+ /* In case of external format, We don't know format yet,
+ * so skip the rest for now.
+ */
+ if (create_info->external_format) {
+ image->external_format = true;
+ *pImage = anv_image_to_handle(image);
+ return VK_SUCCESS;
+ }
+
+ const struct anv_format *format = anv_get_format(image->vk_format);
+ assert(format != NULL);
+
+ const isl_tiling_flags_t isl_tiling_flags =
+ choose_isl_tiling_flags(create_info, isl_mod_info,
+ image->needs_set_tiling);
+
+ image->n_planes = format->n_planes;
+
+ const VkImageFormatListCreateInfoKHR *fmt_list =
+ vk_find_struct_const(pCreateInfo->pNext,
+ IMAGE_FORMAT_LIST_CREATE_INFO_KHR);
+
+ image->ccs_e_compatible =
+ all_formats_ccs_e_compatible(&device->info, fmt_list, image);
uint32_t b;
for_each_bit(b, image->aspects) {
- r = make_surface(device, image, create_info, (1 << b));
+ r = make_surface(device, image, create_info->stride, isl_tiling_flags,
+ create_info->isl_extra_usage_flags, (1 << b));
if (r != VK_SUCCESS)
goto fail;
}
return r;
}
+static struct anv_image *
+anv_swapchain_get_image(VkSwapchainKHR swapchain,
+ uint32_t index)
+{
+ uint32_t n_images = index + 1;
+ VkImage *images = malloc(sizeof(*images) * n_images);
+ VkResult result = wsi_common_get_images(swapchain, &n_images, images);
+
+ if (result != VK_SUCCESS && result != VK_INCOMPLETE) {
+ free(images);
+ return NULL;
+ }
+
+ ANV_FROM_HANDLE(anv_image, image, images[index]);
+ free(images);
+
+ return image;
+}
+
+static VkResult
+anv_image_from_swapchain(VkDevice device,
+ const VkImageCreateInfo *pCreateInfo,
+ const VkImageSwapchainCreateInfoKHR *swapchain_info,
+ const VkAllocationCallbacks *pAllocator,
+ VkImage *pImage)
+{
+ struct anv_image *swapchain_image = anv_swapchain_get_image(swapchain_info->swapchain, 0);
+ assert(swapchain_image);
+
+ assert(swapchain_image->type == pCreateInfo->imageType);
+ assert(swapchain_image->vk_format == pCreateInfo->format);
+ assert(swapchain_image->extent.width == pCreateInfo->extent.width);
+ assert(swapchain_image->extent.height == pCreateInfo->extent.height);
+ assert(swapchain_image->extent.depth == pCreateInfo->extent.depth);
+ assert(swapchain_image->array_size == pCreateInfo->arrayLayers);
+ /* Color attachment is added by the wsi code. */
+ assert(swapchain_image->usage == (pCreateInfo->usage | VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT));
+
+ VkImageCreateInfo local_create_info;
+ local_create_info = *pCreateInfo;
+ local_create_info.pNext = NULL;
+ /* The following parameters are implictly selected by the wsi code. */
+ local_create_info.tiling = VK_IMAGE_TILING_OPTIMAL;
+ local_create_info.samples = VK_SAMPLE_COUNT_1_BIT;
+ local_create_info.usage |= VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT;
+
+ /* If the image has a particular modifier, specify that modifier. */
+ struct wsi_image_create_info local_wsi_info = {
+ .sType = VK_STRUCTURE_TYPE_WSI_IMAGE_CREATE_INFO_MESA,
+ .modifier_count = 1,
+ .modifiers = &swapchain_image->drm_format_mod,
+ };
+ if (swapchain_image->drm_format_mod != DRM_FORMAT_MOD_INVALID)
+ __vk_append_struct(&local_create_info, &local_wsi_info);
+
+ return anv_image_create(device,
+ &(struct anv_image_create_info) {
+ .vk_info = &local_create_info,
+ .external_format = swapchain_image->external_format,
+ },
+ pAllocator,
+ pImage);
+}
+
VkResult
anv_CreateImage(VkDevice device,
const VkImageCreateInfo *pCreateInfo,
const VkAllocationCallbacks *pAllocator,
VkImage *pImage)
{
+ const VkExternalMemoryImageCreateInfo *create_info =
+ vk_find_struct_const(pCreateInfo->pNext, EXTERNAL_MEMORY_IMAGE_CREATE_INFO);
+
+ if (create_info && (create_info->handleTypes &
+ VK_EXTERNAL_MEMORY_HANDLE_TYPE_ANDROID_HARDWARE_BUFFER_BIT_ANDROID))
+ return anv_image_from_external(device, pCreateInfo, create_info,
+ pAllocator, pImage);
+
+ bool use_external_format = false;
+ const VkExternalFormatANDROID *ext_format =
+ vk_find_struct_const(pCreateInfo->pNext, EXTERNAL_FORMAT_ANDROID);
+
+ /* "If externalFormat is zero, the effect is as if the
+ * VkExternalFormatANDROID structure was not present. Otherwise, the image
+ * will have the specified external format."
+ */
+ if (ext_format && ext_format->externalFormat != 0)
+ use_external_format = true;
+
+ const VkNativeBufferANDROID *gralloc_info =
+ vk_find_struct_const(pCreateInfo->pNext, NATIVE_BUFFER_ANDROID);
+ if (gralloc_info)
+ return anv_image_from_gralloc(device, pCreateInfo, gralloc_info,
+ pAllocator, pImage);
+
+ const VkImageSwapchainCreateInfoKHR *swapchain_info =
+ vk_find_struct_const(pCreateInfo->pNext, IMAGE_SWAPCHAIN_CREATE_INFO_KHR);
+ if (swapchain_info && swapchain_info->swapchain != VK_NULL_HANDLE)
+ return anv_image_from_swapchain(device, pCreateInfo, swapchain_info,
+ pAllocator, pImage);
+
return anv_image_create(device,
&(struct anv_image_create_info) {
.vk_info = pCreateInfo,
+ .external_format = use_external_format,
},
pAllocator,
pImage);
if (!image)
return;
+ for (uint32_t p = 0; p < image->n_planes; ++p) {
+ if (anv_image_plane_uses_aux_map(device, image, p) &&
+ image->planes[p].address.bo) {
+ gen_aux_map_unmap_range(device->aux_map_ctx,
+ image->planes[p].aux_map_surface_address,
+ image->planes[p].surface.isl.size_B);
+ }
+ if (image->planes[p].bo_is_owned) {
+ assert(image->planes[p].address.bo != NULL);
+ anv_device_release_bo(device, image->planes[p].address.bo);
+ }
+ }
+
vk_free2(&device->alloc, pAllocator, image);
}
+static void anv_image_bind_memory_plane(struct anv_device *device,
+ struct anv_image *image,
+ uint32_t plane,
+ struct anv_device_memory *memory,
+ uint32_t memory_offset)
+{
+ assert(!image->planes[plane].bo_is_owned);
+
+ if (!memory) {
+ if (anv_image_plane_uses_aux_map(device, image, plane) &&
+ image->planes[plane].address.bo) {
+ gen_aux_map_unmap_range(device->aux_map_ctx,
+ image->planes[plane].aux_map_surface_address,
+ image->planes[plane].surface.isl.size_B);
+ }
+ image->planes[plane].address = ANV_NULL_ADDRESS;
+ return;
+ }
+
+ image->planes[plane].address = (struct anv_address) {
+ .bo = memory->bo,
+ .offset = memory_offset,
+ };
+
+ if (anv_image_plane_uses_aux_map(device, image, plane)) {
+ image->planes[plane].aux_map_surface_address =
+ anv_address_physical(
+ anv_address_add(image->planes[plane].address,
+ image->planes[plane].surface.offset));
+
+ gen_aux_map_add_image(device->aux_map_ctx,
+ &image->planes[plane].surface.isl,
+ image->planes[plane].aux_map_surface_address,
+ anv_address_physical(
+ anv_address_add(image->planes[plane].address,
+ image->planes[plane].aux_surface.offset)));
+ }
+}
+
+/* We are binding AHardwareBuffer. Get a description, resolve the
+ * format and prepare anv_image properly.
+ */
+static void
+resolve_ahw_image(struct anv_device *device,
+ struct anv_image *image,
+ struct anv_device_memory *mem)
+{
+#if defined(ANDROID) && ANDROID_API_LEVEL >= 26
+ assert(mem->ahw);
+ AHardwareBuffer_Desc desc;
+ AHardwareBuffer_describe(mem->ahw, &desc);
+
+ /* Check tiling. */
+ int i915_tiling = anv_gem_get_tiling(device, mem->bo->gem_handle);
+ VkImageTiling vk_tiling;
+ isl_tiling_flags_t isl_tiling_flags = 0;
+
+ switch (i915_tiling) {
+ case I915_TILING_NONE:
+ vk_tiling = VK_IMAGE_TILING_LINEAR;
+ isl_tiling_flags = ISL_TILING_LINEAR_BIT;
+ break;
+ case I915_TILING_X:
+ vk_tiling = VK_IMAGE_TILING_OPTIMAL;
+ isl_tiling_flags = ISL_TILING_X_BIT;
+ break;
+ case I915_TILING_Y:
+ vk_tiling = VK_IMAGE_TILING_OPTIMAL;
+ isl_tiling_flags = ISL_TILING_Y0_BIT;
+ break;
+ case -1:
+ default:
+ unreachable("Invalid tiling flags.");
+ }
+
+ assert(vk_tiling == VK_IMAGE_TILING_LINEAR ||
+ vk_tiling == VK_IMAGE_TILING_OPTIMAL);
+
+ /* Check format. */
+ VkFormat vk_format = vk_format_from_android(desc.format, desc.usage);
+ enum isl_format isl_fmt = anv_get_isl_format(&device->info,
+ vk_format,
+ VK_IMAGE_ASPECT_COLOR_BIT,
+ vk_tiling);
+ assert(isl_fmt != ISL_FORMAT_UNSUPPORTED);
+
+ /* Handle RGB(X)->RGBA fallback. */
+ switch (desc.format) {
+ case AHARDWAREBUFFER_FORMAT_R8G8B8_UNORM:
+ case AHARDWAREBUFFER_FORMAT_R8G8B8X8_UNORM:
+ if (isl_format_is_rgb(isl_fmt))
+ isl_fmt = isl_format_rgb_to_rgba(isl_fmt);
+ break;
+ }
+
+ /* Now we are able to fill anv_image fields properly and create
+ * isl_surface for it.
+ */
+ image->vk_format = vk_format;
+ image->format = anv_get_format(vk_format);
+ image->aspects = vk_format_aspects(image->vk_format);
+ image->n_planes = image->format->n_planes;
+ image->ccs_e_compatible = false;
+
+ uint32_t stride = desc.stride *
+ (isl_format_get_layout(isl_fmt)->bpb / 8);
+
+ uint32_t b;
+ for_each_bit(b, image->aspects) {
+ VkResult r = make_surface(device, image, stride, isl_tiling_flags,
+ ISL_SURF_USAGE_DISABLE_AUX_BIT, (1 << b));
+ assert(r == VK_SUCCESS);
+ }
+#endif
+}
+
VkResult anv_BindImageMemory(
VkDevice _device,
VkImage _image,
VkDeviceMemory _memory,
VkDeviceSize memoryOffset)
{
+ ANV_FROM_HANDLE(anv_device, device, _device);
ANV_FROM_HANDLE(anv_device_memory, mem, _memory);
ANV_FROM_HANDLE(anv_image, image, _image);
- if (mem == NULL) {
- image->bo = NULL;
- image->offset = 0;
- return VK_SUCCESS;
- }
+ if (mem->ahw)
+ resolve_ahw_image(device, image, mem);
- image->bo = mem->bo;
- image->offset = memoryOffset;
+ uint32_t aspect_bit;
+ anv_foreach_image_aspect_bit(aspect_bit, image, image->aspects) {
+ uint32_t plane =
+ anv_image_aspect_to_plane(image->aspects, 1UL << aspect_bit);
+ anv_image_bind_memory_plane(device, image, plane, mem, memoryOffset);
+ }
return VK_SUCCESS;
}
-static void
-anv_surface_get_subresource_layout(struct anv_image *image,
- struct anv_surface *surface,
- const VkImageSubresource *subresource,
- VkSubresourceLayout *layout)
+VkResult anv_BindImageMemory2(
+ VkDevice _device,
+ uint32_t bindInfoCount,
+ const VkBindImageMemoryInfo* pBindInfos)
{
- /* If we are on a non-zero mip level or array slice, we need to
- * calculate a real offset.
- */
- anv_assert(subresource->mipLevel == 0);
- anv_assert(subresource->arrayLayer == 0);
+ ANV_FROM_HANDLE(anv_device, device, _device);
- layout->offset = surface->offset;
- layout->rowPitch = surface->isl.row_pitch;
- layout->depthPitch = isl_surf_get_array_pitch(&surface->isl);
- layout->arrayPitch = isl_surf_get_array_pitch(&surface->isl);
- layout->size = surface->isl.size;
+ for (uint32_t i = 0; i < bindInfoCount; i++) {
+ const VkBindImageMemoryInfo *bind_info = &pBindInfos[i];
+ ANV_FROM_HANDLE(anv_device_memory, mem, bind_info->memory);
+ ANV_FROM_HANDLE(anv_image, image, bind_info->image);
+
+ /* Resolve will alter the image's aspects, do this first. */
+ if (mem && mem->ahw)
+ resolve_ahw_image(device, image, mem);
+
+ VkImageAspectFlags aspects = image->aspects;
+ vk_foreach_struct_const(s, bind_info->pNext) {
+ switch (s->sType) {
+ case VK_STRUCTURE_TYPE_BIND_IMAGE_PLANE_MEMORY_INFO: {
+ const VkBindImagePlaneMemoryInfo *plane_info =
+ (const VkBindImagePlaneMemoryInfo *) s;
+
+ aspects = plane_info->planeAspect;
+ break;
+ }
+ case VK_STRUCTURE_TYPE_BIND_IMAGE_MEMORY_SWAPCHAIN_INFO_KHR: {
+ const VkBindImageMemorySwapchainInfoKHR *swapchain_info =
+ (const VkBindImageMemorySwapchainInfoKHR *) s;
+ struct anv_image *swapchain_image =
+ anv_swapchain_get_image(swapchain_info->swapchain,
+ swapchain_info->imageIndex);
+ assert(swapchain_image);
+ assert(image->aspects == swapchain_image->aspects);
+ assert(mem == NULL);
+
+ uint32_t aspect_bit;
+ anv_foreach_image_aspect_bit(aspect_bit, image, aspects) {
+ uint32_t plane =
+ anv_image_aspect_to_plane(image->aspects, 1UL << aspect_bit);
+ struct anv_device_memory mem = {
+ .bo = swapchain_image->planes[plane].address.bo,
+ };
+ anv_image_bind_memory_plane(device, image, plane,
+ &mem, bind_info->memoryOffset);
+ }
+ break;
+ }
+ default:
+ anv_debug_ignored_stype(s->sType);
+ break;
+ }
+ }
+
+ /* VkBindImageMemorySwapchainInfoKHR requires memory to be
+ * VK_NULL_HANDLE. In such case, just carry one with the next bind
+ * item.
+ */
+ if (!mem)
+ continue;
+
+ uint32_t aspect_bit;
+ anv_foreach_image_aspect_bit(aspect_bit, image, aspects) {
+ uint32_t plane =
+ anv_image_aspect_to_plane(image->aspects, 1UL << aspect_bit);
+ anv_image_bind_memory_plane(device, image, plane,
+ mem, bind_info->memoryOffset);
+ }
+ }
+
+ return VK_SUCCESS;
}
void anv_GetImageSubresourceLayout(
VkDevice device,
VkImage _image,
- const VkImageSubresource* pSubresource,
- VkSubresourceLayout* pLayout)
+ const VkImageSubresource* subresource,
+ VkSubresourceLayout* layout)
{
ANV_FROM_HANDLE(anv_image, image, _image);
- assert(__builtin_popcount(pSubresource->aspectMask) == 1);
+ const struct anv_surface *surface;
+ if (subresource->aspectMask == VK_IMAGE_ASPECT_PLANE_1_BIT &&
+ image->drm_format_mod != DRM_FORMAT_MOD_INVALID &&
+ isl_drm_modifier_has_aux(image->drm_format_mod))
+ surface = &image->planes[0].aux_surface;
+ else
+ surface = get_surface(image, subresource->aspectMask);
- switch (pSubresource->aspectMask) {
- case VK_IMAGE_ASPECT_COLOR_BIT:
- anv_surface_get_subresource_layout(image, &image->color_surface,
- pSubresource, pLayout);
- break;
- case VK_IMAGE_ASPECT_DEPTH_BIT:
- anv_surface_get_subresource_layout(image, &image->depth_surface,
- pSubresource, pLayout);
- break;
- case VK_IMAGE_ASPECT_STENCIL_BIT:
- anv_surface_get_subresource_layout(image, &image->stencil_surface,
- pSubresource, pLayout);
- break;
- default:
- assert(!"Invalid image aspect");
+ assert(__builtin_popcount(subresource->aspectMask) == 1);
+
+ layout->offset = surface->offset;
+ layout->rowPitch = surface->isl.row_pitch_B;
+ layout->depthPitch = isl_surf_get_array_pitch(&surface->isl);
+ layout->arrayPitch = isl_surf_get_array_pitch(&surface->isl);
+
+ if (subresource->mipLevel > 0 || subresource->arrayLayer > 0) {
+ assert(surface->isl.tiling == ISL_TILING_LINEAR);
+
+ uint32_t offset_B;
+ isl_surf_get_image_offset_B_tile_sa(&surface->isl,
+ subresource->mipLevel,
+ subresource->arrayLayer,
+ 0 /* logical_z_offset_px */,
+ &offset_B, NULL, NULL);
+ layout->offset += offset_B;
+ layout->size = layout->rowPitch * anv_minify(image->extent.height,
+ subresource->mipLevel);
+ } else {
+ layout->size = surface->isl.size_B;
}
}
*
* @param devinfo The device information of the Intel GPU.
* @param image The image that may contain a collection of buffers.
- * @param aspects The aspect(s) of the image to be accessed.
+ * @param aspect The aspect of the image to be accessed.
* @param layout The current layout of the image aspect(s).
*
* @return The primary buffer that should be used for the given layout.
enum isl_aux_usage
anv_layout_to_aux_usage(const struct gen_device_info * const devinfo,
const struct anv_image * const image,
- const VkImageAspectFlags aspects,
+ const VkImageAspectFlagBits aspect,
const VkImageLayout layout)
{
/* Validate the inputs. */
/* The layout of a NULL image is not properly defined. */
assert(image != NULL);
- /* The aspects must be a subset of the image aspects. */
- assert(aspects & image->aspects && aspects <= image->aspects);
+ /* The aspect must be exactly one of the image aspects. */
+ assert(util_bitcount(aspect) == 1 && (aspect & image->aspects));
/* Determine the optimal buffer. */
+ uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
+
/* If there is no auxiliary surface allocated, we must use the one and only
* main buffer.
*/
- if (image->aux_surface.isl.size == 0)
+ if (image->planes[plane].aux_surface.isl.size_B == 0)
return ISL_AUX_USAGE_NONE;
/* All images that use an auxiliary surface are required to be tiled. */
- assert(image->tiling == VK_IMAGE_TILING_OPTIMAL);
+ assert(image->planes[plane].surface.isl.tiling != ISL_TILING_LINEAR);
- /* On BDW+, when clearing the stencil aspect of a depth stencil image,
- * the HiZ buffer allows us to record the clear with a relatively small
- * number of packets. Prior to BDW, the HiZ buffer provides no known benefit
- * to the stencil aspect.
- */
- if (devinfo->gen < 8 && aspects == VK_IMAGE_ASPECT_STENCIL_BIT)
- return ISL_AUX_USAGE_NONE;
-
- const bool color_aspect = aspects == VK_IMAGE_ASPECT_COLOR_BIT;
-
- /* The following switch currently only handles depth stencil aspects.
- * TODO: Handle the color aspect.
- */
- if (color_aspect)
- return image->aux_usage;
+ /* Stencil has no aux */
+ assert(aspect != VK_IMAGE_ASPECT_STENCIL_BIT);
switch (layout) {
/* Transfer Layouts
- *
- * This buffer could be a depth buffer used in a transfer operation. BLORP
- * currently doesn't use HiZ for transfer operations so we must use the main
- * buffer for this layout. TODO: Enable HiZ in BLORP.
*/
case VK_IMAGE_LAYOUT_GENERAL:
case VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL:
- case VK_IMAGE_LAYOUT_TRANSFER_SRC_OPTIMAL:
- return ISL_AUX_USAGE_NONE;
+ if (aspect == VK_IMAGE_ASPECT_DEPTH_BIT) {
+ /* This buffer could be a depth buffer used in a transfer operation.
+ * BLORP currently doesn't use HiZ for transfer operations so we must
+ * use the main buffer for this layout. TODO: Enable HiZ in BLORP.
+ */
+ assert(image->planes[plane].aux_usage == ISL_AUX_USAGE_HIZ);
+ return ISL_AUX_USAGE_NONE;
+ } else {
+ assert(image->aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV);
+ return image->planes[plane].aux_usage;
+ }
/* Sampling Layouts */
+ case VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_OPTIMAL_KHR:
case VK_IMAGE_LAYOUT_DEPTH_STENCIL_READ_ONLY_OPTIMAL:
- assert(!color_aspect);
+ case VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL:
+ assert((image->aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) == 0);
/* Fall-through */
+ case VK_IMAGE_LAYOUT_TRANSFER_SRC_OPTIMAL:
case VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL:
- if (anv_can_sample_with_hiz(devinfo, aspects, image->samples))
- return ISL_AUX_USAGE_HIZ;
- else
- return ISL_AUX_USAGE_NONE;
+ if (aspect == VK_IMAGE_ASPECT_DEPTH_BIT) {
+ if (anv_can_sample_with_hiz(devinfo, image))
+ return ISL_AUX_USAGE_HIZ;
+ else
+ return ISL_AUX_USAGE_NONE;
+ } else {
+ return image->planes[plane].aux_usage;
+ }
- case VK_IMAGE_LAYOUT_PRESENT_SRC_KHR:
- assert(color_aspect);
+ case VK_IMAGE_LAYOUT_STENCIL_READ_ONLY_OPTIMAL_KHR:
+ return ISL_AUX_USAGE_NONE;
- /* On SKL+, the render buffer can be decompressed by the presentation
- * engine. Support for this feature has not yet landed in the wider
- * ecosystem. TODO: Update this code when support lands.
- *
- * From the BDW PRM, Vol 7, Render Target Resolve:
- *
- * If the MCS is enabled on a non-multisampled render target, the
- * render target must be resolved before being used for other
- * purposes (display, texture, CPU lock) The clear value from
- * SURFACE_STATE is written into pixels in the render target
- * indicated as clear in the MCS.
- *
- * Pre-SKL, the render buffer must be resolved before being used for
- * presentation. We can infer that the auxiliary buffer is not used.
+
+ case VK_IMAGE_LAYOUT_PRESENT_SRC_KHR: {
+ assert(image->aspects == VK_IMAGE_ASPECT_COLOR_BIT);
+
+ /* When handing the image off to the presentation engine, we need to
+ * ensure that things are properly resolved. For images with no
+ * modifier, we assume that they follow the old rules and always need
+ * a full resolve because the PE doesn't understand any form of
+ * compression. For images with modifiers, we use the aux usage from
+ * the modifier.
*/
- return ISL_AUX_USAGE_NONE;
+ const struct isl_drm_modifier_info *mod_info =
+ isl_drm_modifier_get_info(image->drm_format_mod);
+ return mod_info ? mod_info->aux_usage : ISL_AUX_USAGE_NONE;
+ }
/* Rendering Layouts */
case VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL:
- assert(color_aspect);
- unreachable("Color images are not yet supported.");
+ assert(aspect & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV);
+ /* fall-through */
+ case VK_IMAGE_LAYOUT_STENCIL_ATTACHMENT_OPTIMAL_KHR:
+ if (image->planes[plane].aux_usage == ISL_AUX_USAGE_NONE) {
+ assert(image->samples == 1);
+ return ISL_AUX_USAGE_CCS_D;
+ } else {
+ assert(image->planes[plane].aux_usage != ISL_AUX_USAGE_CCS_D);
+ return image->planes[plane].aux_usage;
+ }
+ case VK_IMAGE_LAYOUT_DEPTH_ATTACHMENT_OPTIMAL_KHR:
case VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL:
- assert(!color_aspect);
+ case VK_IMAGE_LAYOUT_DEPTH_ATTACHMENT_STENCIL_READ_ONLY_OPTIMAL:
+ assert(aspect == VK_IMAGE_ASPECT_DEPTH_BIT);
return ISL_AUX_USAGE_HIZ;
case VK_IMAGE_LAYOUT_SHARED_PRESENT_KHR:
unreachable("VK_KHR_shared_presentable_image is unsupported");
+
+ case VK_IMAGE_LAYOUT_FRAGMENT_DENSITY_MAP_OPTIMAL_EXT:
+ unreachable("VK_EXT_fragment_density_map is unsupported");
+
+ case VK_IMAGE_LAYOUT_SHADING_RATE_OPTIMAL_NV:
+ unreachable("VK_NV_shading_rate_image is unsupported");
}
/* If the layout isn't recognized in the exhaustive switch above, the
unreachable("layout is not a VkImageLayout enumeration member.");
}
+/**
+ * This function returns the level of unresolved fast-clear support of the
+ * given image in the given VkImageLayout.
+ *
+ * @param devinfo The device information of the Intel GPU.
+ * @param image The image that may contain a collection of buffers.
+ * @param aspect The aspect of the image to be accessed.
+ * @param layout The current layout of the image aspect(s).
+ */
+enum anv_fast_clear_type
+anv_layout_to_fast_clear_type(const struct gen_device_info * const devinfo,
+ const struct anv_image * const image,
+ const VkImageAspectFlagBits aspect,
+ const VkImageLayout layout)
+{
+ if (INTEL_DEBUG & DEBUG_NO_FAST_CLEAR)
+ return ANV_FAST_CLEAR_NONE;
+
+ /* The aspect must be exactly one of the image aspects. */
+ assert(util_bitcount(aspect) == 1 && (aspect & image->aspects));
+
+ uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
+
+ /* If there is no auxiliary surface allocated, there are no fast-clears */
+ if (image->planes[plane].aux_surface.isl.size_B == 0)
+ return ANV_FAST_CLEAR_NONE;
+
+ /* All images that use an auxiliary surface are required to be tiled. */
+ assert(image->planes[plane].surface.isl.tiling != ISL_TILING_LINEAR);
+
+ /* Stencil has no aux */
+ assert(aspect != VK_IMAGE_ASPECT_STENCIL_BIT);
+
+ if (aspect == VK_IMAGE_ASPECT_DEPTH_BIT) {
+ /* For depth images (with HiZ), the layout supports fast-clears if and
+ * only if it supports HiZ. However, we only support fast-clears to the
+ * default depth value.
+ */
+ enum isl_aux_usage aux_usage =
+ anv_layout_to_aux_usage(devinfo, image, aspect, layout);
+ return aux_usage == ISL_AUX_USAGE_HIZ ?
+ ANV_FAST_CLEAR_DEFAULT_VALUE : ANV_FAST_CLEAR_NONE;
+ }
+
+ assert(image->aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV);
+
+ /* We don't support MSAA fast-clears on Ivybridge or Bay Trail because they
+ * lack the MI ALU which we need to determine the predicates.
+ */
+ if (devinfo->gen == 7 && !devinfo->is_haswell && image->samples > 1)
+ return ANV_FAST_CLEAR_NONE;
+
+ switch (layout) {
+ case VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL:
+ return ANV_FAST_CLEAR_ANY;
+
+ case VK_IMAGE_LAYOUT_PRESENT_SRC_KHR: {
+ assert(image->aspects == VK_IMAGE_ASPECT_COLOR_BIT);
+#ifndef NDEBUG
+ /* We do not yet support any modifiers which support clear color so we
+ * just always return NONE. One day, this will change.
+ */
+ const struct isl_drm_modifier_info *mod_info =
+ isl_drm_modifier_get_info(image->drm_format_mod);
+ assert(!mod_info || !mod_info->supports_clear_color);
+#endif
+ return ANV_FAST_CLEAR_NONE;
+ }
+
+ default:
+ /* If the image has MCS or CCS_E enabled all the time then we can use
+ * fast-clear as long as the clear color is the default value of zero
+ * since this is the default value we program into every surface state
+ * used for texturing.
+ */
+ if (image->planes[plane].aux_usage == ISL_AUX_USAGE_MCS ||
+ image->planes[plane].aux_usage == ISL_AUX_USAGE_CCS_E)
+ return ANV_FAST_CLEAR_DEFAULT_VALUE;
+ else
+ return ANV_FAST_CLEAR_NONE;
+ }
+}
+
static struct anv_state
alloc_surface_state(struct anv_device *device)
}
}
+void
+anv_image_fill_surface_state(struct anv_device *device,
+ const struct anv_image *image,
+ VkImageAspectFlagBits aspect,
+ const struct isl_view *view_in,
+ isl_surf_usage_flags_t view_usage,
+ enum isl_aux_usage aux_usage,
+ const union isl_color_value *clear_color,
+ enum anv_image_view_state_flags flags,
+ struct anv_surface_state *state_inout,
+ struct brw_image_param *image_param_out)
+{
+ uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
+
+ const struct anv_surface *surface = &image->planes[plane].surface,
+ *aux_surface = &image->planes[plane].aux_surface;
+
+ struct isl_view view = *view_in;
+ view.usage |= view_usage;
+
+ /* For texturing with VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL from a
+ * compressed surface with a shadow surface, we use the shadow instead of
+ * the primary surface. The shadow surface will be tiled, unlike the main
+ * surface, so it should get significantly better performance.
+ */
+ if (image->planes[plane].shadow_surface.isl.size_B > 0 &&
+ isl_format_is_compressed(view.format) &&
+ (flags & ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL)) {
+ assert(isl_format_is_compressed(surface->isl.format));
+ assert(surface->isl.tiling == ISL_TILING_LINEAR);
+ assert(image->planes[plane].shadow_surface.isl.tiling != ISL_TILING_LINEAR);
+ surface = &image->planes[plane].shadow_surface;
+ }
+
+ /* For texturing from stencil on gen7, we have to sample from a shadow
+ * surface because we don't support W-tiling in the sampler.
+ */
+ if (image->planes[plane].shadow_surface.isl.size_B > 0 &&
+ aspect == VK_IMAGE_ASPECT_STENCIL_BIT) {
+ assert(device->info.gen == 7);
+ assert(view_usage & ISL_SURF_USAGE_TEXTURE_BIT);
+ surface = &image->planes[plane].shadow_surface;
+ }
+
+ if (view_usage == ISL_SURF_USAGE_RENDER_TARGET_BIT)
+ view.swizzle = anv_swizzle_for_render(view.swizzle);
+
+ /* On Ivy Bridge and Bay Trail we do the swizzle in the shader */
+ if (device->info.gen == 7 && !device->info.is_haswell)
+ view.swizzle = ISL_SWIZZLE_IDENTITY;
+
+ /* If this is a HiZ buffer we can sample from with a programmable clear
+ * value (SKL+), define the clear value to the optimal constant.
+ */
+ union isl_color_value default_clear_color = { .u32 = { 0, } };
+ if (device->info.gen >= 9 && aux_usage == ISL_AUX_USAGE_HIZ)
+ default_clear_color.f32[0] = ANV_HZ_FC_VAL;
+ if (!clear_color)
+ clear_color = &default_clear_color;
+
+ const struct anv_address address =
+ anv_address_add(image->planes[plane].address, surface->offset);
+
+ if (view_usage == ISL_SURF_USAGE_STORAGE_BIT &&
+ !(flags & ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY) &&
+ !isl_has_matching_typed_storage_image_format(&device->info,
+ view.format)) {
+ /* In this case, we are a writeable storage buffer which needs to be
+ * lowered to linear. All tiling and offset calculations will be done in
+ * the shader.
+ */
+ assert(aux_usage == ISL_AUX_USAGE_NONE);
+ isl_buffer_fill_state(&device->isl_dev, state_inout->state.map,
+ .address = anv_address_physical(address),
+ .size_B = surface->isl.size_B,
+ .format = ISL_FORMAT_RAW,
+ .swizzle = ISL_SWIZZLE_IDENTITY,
+ .stride_B = 1,
+ .mocs = anv_mocs_for_bo(device, address.bo));
+ state_inout->address = address,
+ state_inout->aux_address = ANV_NULL_ADDRESS;
+ state_inout->clear_address = ANV_NULL_ADDRESS;
+ } else {
+ if (view_usage == ISL_SURF_USAGE_STORAGE_BIT &&
+ !(flags & ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY)) {
+ /* Typed surface reads support a very limited subset of the shader
+ * image formats. Translate it into the closest format the hardware
+ * supports.
+ */
+ assert(aux_usage == ISL_AUX_USAGE_NONE);
+ view.format = isl_lower_storage_image_format(&device->info,
+ view.format);
+ }
+
+ const struct isl_surf *isl_surf = &surface->isl;
+
+ struct isl_surf tmp_surf;
+ uint32_t offset_B = 0, tile_x_sa = 0, tile_y_sa = 0;
+ if (isl_format_is_compressed(surface->isl.format) &&
+ !isl_format_is_compressed(view.format)) {
+ /* We're creating an uncompressed view of a compressed surface. This
+ * is allowed but only for a single level/layer.
+ */
+ assert(surface->isl.samples == 1);
+ assert(view.levels == 1);
+ assert(view.array_len == 1);
+
+ isl_surf_get_image_surf(&device->isl_dev, isl_surf,
+ view.base_level,
+ surface->isl.dim == ISL_SURF_DIM_3D ?
+ 0 : view.base_array_layer,
+ surface->isl.dim == ISL_SURF_DIM_3D ?
+ view.base_array_layer : 0,
+ &tmp_surf,
+ &offset_B, &tile_x_sa, &tile_y_sa);
+
+ /* The newly created image represents the one subimage we're
+ * referencing with this view so it only has one array slice and
+ * miplevel.
+ */
+ view.base_array_layer = 0;
+ view.base_level = 0;
+
+ /* We're making an uncompressed view here. The image dimensions need
+ * to be scaled down by the block size.
+ */
+ const struct isl_format_layout *fmtl =
+ isl_format_get_layout(surface->isl.format);
+ tmp_surf.logical_level0_px =
+ isl_surf_get_logical_level0_el(&tmp_surf);
+ tmp_surf.phys_level0_sa = isl_surf_get_phys_level0_el(&tmp_surf);
+ tmp_surf.format = view.format;
+ tile_x_sa /= fmtl->bw;
+ tile_y_sa /= fmtl->bh;
+
+ isl_surf = &tmp_surf;
+
+ if (device->info.gen <= 8) {
+ assert(surface->isl.tiling == ISL_TILING_LINEAR);
+ assert(tile_x_sa == 0);
+ assert(tile_y_sa == 0);
+ }
+ }
+
+ state_inout->address = anv_address_add(address, offset_B);
+
+ struct anv_address aux_address = ANV_NULL_ADDRESS;
+ if (aux_usage != ISL_AUX_USAGE_NONE) {
+ aux_address = anv_address_add(image->planes[plane].address,
+ aux_surface->offset);
+ }
+ state_inout->aux_address = aux_address;
+
+ struct anv_address clear_address = ANV_NULL_ADDRESS;
+ if (device->info.gen >= 10 && aux_usage != ISL_AUX_USAGE_NONE) {
+ if (aux_usage == ISL_AUX_USAGE_HIZ) {
+ clear_address = (struct anv_address) {
+ .bo = device->hiz_clear_bo,
+ .offset = 0,
+ };
+ } else {
+ clear_address = anv_image_get_clear_color_addr(device, image, aspect);
+ }
+ }
+ state_inout->clear_address = clear_address;
+
+ isl_surf_fill_state(&device->isl_dev, state_inout->state.map,
+ .surf = isl_surf,
+ .view = &view,
+ .address = anv_address_physical(state_inout->address),
+ .clear_color = *clear_color,
+ .aux_surf = &aux_surface->isl,
+ .aux_usage = aux_usage,
+ .aux_address = anv_address_physical(aux_address),
+ .clear_address = anv_address_physical(clear_address),
+ .use_clear_address = !anv_address_is_null(clear_address),
+ .mocs = anv_mocs_for_bo(device,
+ state_inout->address.bo),
+ .x_offset_sa = tile_x_sa,
+ .y_offset_sa = tile_y_sa);
+
+ /* With the exception of gen8, the bottom 12 bits of the MCS base address
+ * are used to store other information. This should be ok, however,
+ * because the surface buffer addresses are always 4K page aligned.
+ */
+ uint32_t *aux_addr_dw = state_inout->state.map +
+ device->isl_dev.ss.aux_addr_offset;
+ assert((aux_address.offset & 0xfff) == 0);
+ state_inout->aux_address.offset |= *aux_addr_dw & 0xfff;
+
+ if (device->info.gen >= 10 && clear_address.bo) {
+ uint32_t *clear_addr_dw = state_inout->state.map +
+ device->isl_dev.ss.clear_color_state_offset;
+ assert((clear_address.offset & 0x3f) == 0);
+ state_inout->clear_address.offset |= *clear_addr_dw & 0x3f;
+ }
+ }
+
+ if (image_param_out) {
+ assert(view_usage == ISL_SURF_USAGE_STORAGE_BIT);
+ isl_surf_fill_image_param(&device->isl_dev, image_param_out,
+ &surface->isl, &view);
+ }
+}
+
+static VkImageAspectFlags
+remap_aspect_flags(VkImageAspectFlags view_aspects)
+{
+ if (view_aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) {
+ if (util_bitcount(view_aspects) == 1)
+ return VK_IMAGE_ASPECT_COLOR_BIT;
+
+ VkImageAspectFlags color_aspects = 0;
+ for (uint32_t i = 0; i < util_bitcount(view_aspects); i++)
+ color_aspects |= VK_IMAGE_ASPECT_PLANE_0_BIT << i;
+ return color_aspects;
+ }
+ /* No special remapping needed for depth & stencil aspects. */
+ return view_aspects;
+}
+
+static uint32_t
+anv_image_aspect_get_planes(VkImageAspectFlags aspect_mask)
+{
+ uint32_t planes = 0;
+
+ if (aspect_mask & (VK_IMAGE_ASPECT_COLOR_BIT |
+ VK_IMAGE_ASPECT_DEPTH_BIT |
+ VK_IMAGE_ASPECT_STENCIL_BIT |
+ VK_IMAGE_ASPECT_PLANE_0_BIT))
+ planes++;
+ if (aspect_mask & VK_IMAGE_ASPECT_PLANE_1_BIT)
+ planes++;
+ if (aspect_mask & VK_IMAGE_ASPECT_PLANE_2_BIT)
+ planes++;
+
+ if ((aspect_mask & VK_IMAGE_ASPECT_DEPTH_BIT) != 0 &&
+ (aspect_mask & VK_IMAGE_ASPECT_STENCIL_BIT) != 0)
+ planes++;
+
+ return planes;
+}
VkResult
anv_CreateImageView(VkDevice _device,
ANV_FROM_HANDLE(anv_image, image, pCreateInfo->image);
struct anv_image_view *iview;
- iview = vk_alloc2(&device->alloc, pAllocator, sizeof(*iview), 8,
+ iview = vk_zalloc2(&device->alloc, pAllocator, sizeof(*iview), 8,
VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
if (iview == NULL)
return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
assert(range->layerCount > 0);
assert(range->baseMipLevel < image->levels);
- assert(image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
- VK_IMAGE_USAGE_STORAGE_BIT |
- VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT |
- VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT));
+
+ /* Check if a conversion info was passed. */
+ const struct anv_format *conv_format = NULL;
+ const VkSamplerYcbcrConversionInfo *conv_info =
+ vk_find_struct_const(pCreateInfo->pNext, SAMPLER_YCBCR_CONVERSION_INFO);
+
+ /* If image has an external format, the pNext chain must contain an instance of
+ * VKSamplerYcbcrConversionInfo with a conversion object created with the same
+ * external format as image."
+ */
+ assert(!image->external_format || conv_info);
+
+ if (conv_info) {
+ ANV_FROM_HANDLE(anv_ycbcr_conversion, conversion, conv_info->conversion);
+ conv_format = conversion->format;
+ }
+
+ VkImageUsageFlags image_usage = 0;
+ if (range->aspectMask & ~VK_IMAGE_ASPECT_STENCIL_BIT)
+ image_usage |= image->usage;
+ if (range->aspectMask & VK_IMAGE_ASPECT_STENCIL_BIT)
+ image_usage |= image->stencil_usage;
+
+ const VkImageViewUsageCreateInfo *usage_info =
+ vk_find_struct_const(pCreateInfo, IMAGE_VIEW_USAGE_CREATE_INFO);
+ VkImageUsageFlags view_usage = usage_info ? usage_info->usage : image_usage;
+
+ /* View usage should be a subset of image usage */
+ assert((view_usage & ~image_usage) == 0);
+ assert(view_usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
+ VK_IMAGE_USAGE_STORAGE_BIT |
+ VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT |
+ VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT |
+ VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT));
switch (image->type) {
default:
break;
}
- const struct anv_surface *surface =
- anv_image_get_surface_for_aspect_mask(image, range->aspectMask);
+ /* First expand aspects to the image's ones (for example
+ * VK_IMAGE_ASPECT_COLOR_BIT will be converted to
+ * VK_IMAGE_ASPECT_PLANE_0_BIT | VK_IMAGE_ASPECT_PLANE_1_BIT |
+ * VK_IMAGE_ASPECT_PLANE_2_BIT for an image of format
+ * VK_FORMAT_G8_B8_R8_3PLANE_420_UNORM.
+ */
+ VkImageAspectFlags expanded_aspects =
+ anv_image_expand_aspects(image, range->aspectMask);
iview->image = image;
- iview->bo = image->bo;
- iview->offset = image->offset + surface->offset;
- iview->aspect_mask = pCreateInfo->subresourceRange.aspectMask;
+ /* Remap the expanded aspects for the image view. For example if only
+ * VK_IMAGE_ASPECT_PLANE_1_BIT was given in range->aspectMask, we will
+ * convert it to VK_IMAGE_ASPECT_COLOR_BIT since from the point of view of
+ * the image view, it only has a single plane.
+ */
+ iview->aspect_mask = remap_aspect_flags(expanded_aspects);
+ iview->n_planes = anv_image_aspect_get_planes(iview->aspect_mask);
iview->vk_format = pCreateInfo->format;
- struct anv_format format = anv_get_format(&device->info, pCreateInfo->format,
- range->aspectMask, image->tiling);
-
- iview->isl = (struct isl_view) {
- .format = format.isl_format,
- .base_level = range->baseMipLevel,
- .levels = anv_get_levelCount(image, range),
- .base_array_layer = range->baseArrayLayer,
- .array_len = anv_get_layerCount(image, range),
- .swizzle = {
- .r = remap_swizzle(pCreateInfo->components.r,
- VK_COMPONENT_SWIZZLE_R, format.swizzle),
- .g = remap_swizzle(pCreateInfo->components.g,
- VK_COMPONENT_SWIZZLE_G, format.swizzle),
- .b = remap_swizzle(pCreateInfo->components.b,
- VK_COMPONENT_SWIZZLE_B, format.swizzle),
- .a = remap_swizzle(pCreateInfo->components.a,
- VK_COMPONENT_SWIZZLE_A, format.swizzle),
- },
- };
+ /* "If image has an external format, format must be VK_FORMAT_UNDEFINED." */
+ assert(!image->external_format || pCreateInfo->format == VK_FORMAT_UNDEFINED);
+
+ /* Format is undefined, this can happen when using external formats. Set
+ * view format from the passed conversion info.
+ */
+ if (iview->vk_format == VK_FORMAT_UNDEFINED && conv_format)
+ iview->vk_format = conv_format->vk_format;
iview->extent = (VkExtent3D) {
.width = anv_minify(image->extent.width , range->baseMipLevel),
.depth = anv_minify(image->extent.depth , range->baseMipLevel),
};
- if (pCreateInfo->viewType == VK_IMAGE_VIEW_TYPE_3D) {
- iview->isl.base_array_layer = 0;
- iview->isl.array_len = iview->extent.depth;
- }
-
- if (pCreateInfo->viewType == VK_IMAGE_VIEW_TYPE_CUBE ||
- pCreateInfo->viewType == VK_IMAGE_VIEW_TYPE_CUBE_ARRAY) {
- iview->isl.usage = ISL_SURF_USAGE_CUBE_BIT;
- } else {
- iview->isl.usage = 0;
- }
-
- /* Input attachment surfaces for color are allocated and filled
- * out at BeginRenderPass time because they need compression information.
- * Compression is not yet enabled for depth textures and stencil doesn't
- * allow compression so we can just use the texture surface state from the
- * view.
+ /* Now go through the underlying image selected planes (computed in
+ * expanded_aspects) and map them to planes in the image view.
*/
- if (image->usage & VK_IMAGE_USAGE_SAMPLED_BIT ||
- (image->usage & VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT &&
- !(iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT))) {
- iview->sampler_surface_state = alloc_surface_state(device);
- iview->no_aux_sampler_surface_state = alloc_surface_state(device);
-
- /* Sampling is performed in one of two buffer configurations in anv: with
- * an auxiliary buffer or without it. Sampler states aren't always needed
- * for both configurations, but are currently created unconditionally for
- * simplicity.
- *
- * TODO: Consider allocating each surface state only when necessary.
- */
-
- /* Create a sampler state with the optimal aux_usage for sampling. This
- * may use the aux_buffer.
- */
- const enum isl_aux_usage surf_usage =
- anv_layout_to_aux_usage(&device->info, image, iview->aspect_mask,
- VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL);
-
- /* If this is a HiZ buffer we can sample from with a programmable clear
- * value (SKL+), define the clear value to the optimal constant.
- */
- const float red_clear_color = surf_usage == ISL_AUX_USAGE_HIZ &&
- device->info.gen >= 9 ?
- ANV_HZ_FC_VAL : 0.0f;
-
- struct isl_view view = iview->isl;
- view.usage |= ISL_SURF_USAGE_TEXTURE_BIT;
- isl_surf_fill_state(&device->isl_dev,
- iview->sampler_surface_state.map,
- .surf = &surface->isl,
- .view = &view,
- .clear_color.f32 = { red_clear_color,},
- .aux_surf = &image->aux_surface.isl,
- .aux_usage = surf_usage,
- .mocs = device->default_mocs);
-
- /* Create a sampler state that only uses the main buffer. */
- isl_surf_fill_state(&device->isl_dev,
- iview->no_aux_sampler_surface_state.map,
- .surf = &surface->isl,
- .view = &view,
- .mocs = device->default_mocs);
-
- anv_state_flush(device, iview->sampler_surface_state);
- anv_state_flush(device, iview->no_aux_sampler_surface_state);
- } else {
- iview->sampler_surface_state.alloc_size = 0;
- iview->no_aux_sampler_surface_state.alloc_size = 0;
- }
-
- /* NOTE: This one needs to go last since it may stomp isl_view.format */
- if (image->usage & VK_IMAGE_USAGE_STORAGE_BIT) {
- iview->storage_surface_state = alloc_surface_state(device);
- iview->writeonly_storage_surface_state = alloc_surface_state(device);
-
- struct isl_view view = iview->isl;
- view.usage |= ISL_SURF_USAGE_STORAGE_BIT;
-
- /* Write-only accesses always used a typed write instruction and should
- * therefore use the real format.
- */
- isl_surf_fill_state(&device->isl_dev,
- iview->writeonly_storage_surface_state.map,
- .surf = &surface->isl,
- .view = &view,
- .aux_surf = &image->aux_surface.isl,
- .aux_usage = image->aux_usage,
- .mocs = device->default_mocs);
+ uint32_t iaspect_bit, vplane = 0;
+ anv_foreach_image_aspect_bit(iaspect_bit, image, expanded_aspects) {
+ uint32_t iplane =
+ anv_image_aspect_to_plane(image->aspects, 1UL << iaspect_bit);
+ VkImageAspectFlags vplane_aspect =
+ anv_plane_to_aspect(iview->aspect_mask, vplane);
+ struct anv_format_plane format =
+ anv_get_format_plane(&device->info, iview->vk_format,
+ vplane_aspect, image->tiling);
+
+ iview->planes[vplane].image_plane = iplane;
+
+ iview->planes[vplane].isl = (struct isl_view) {
+ .format = format.isl_format,
+ .base_level = range->baseMipLevel,
+ .levels = anv_get_levelCount(image, range),
+ .base_array_layer = range->baseArrayLayer,
+ .array_len = anv_get_layerCount(image, range),
+ .swizzle = {
+ .r = remap_swizzle(pCreateInfo->components.r,
+ VK_COMPONENT_SWIZZLE_R, format.swizzle),
+ .g = remap_swizzle(pCreateInfo->components.g,
+ VK_COMPONENT_SWIZZLE_G, format.swizzle),
+ .b = remap_swizzle(pCreateInfo->components.b,
+ VK_COMPONENT_SWIZZLE_B, format.swizzle),
+ .a = remap_swizzle(pCreateInfo->components.a,
+ VK_COMPONENT_SWIZZLE_A, format.swizzle),
+ },
+ };
+
+ if (pCreateInfo->viewType == VK_IMAGE_VIEW_TYPE_3D) {
+ iview->planes[vplane].isl.base_array_layer = 0;
+ iview->planes[vplane].isl.array_len = iview->extent.depth;
+ }
- if (isl_has_matching_typed_storage_image_format(&device->info,
- format.isl_format)) {
- /* Typed surface reads support a very limited subset of the shader
- * image formats. Translate it into the closest format the hardware
- * supports.
- */
- view.format = isl_lower_storage_image_format(&device->info,
- format.isl_format);
-
- isl_surf_fill_state(&device->isl_dev,
- iview->storage_surface_state.map,
- .surf = &surface->isl,
- .view = &view,
- .aux_surf = &image->aux_surface.isl,
- .aux_usage = image->aux_usage,
- .mocs = device->default_mocs);
+ if (pCreateInfo->viewType == VK_IMAGE_VIEW_TYPE_CUBE ||
+ pCreateInfo->viewType == VK_IMAGE_VIEW_TYPE_CUBE_ARRAY) {
+ iview->planes[vplane].isl.usage = ISL_SURF_USAGE_CUBE_BIT;
} else {
- anv_fill_buffer_surface_state(device, iview->storage_surface_state,
- ISL_FORMAT_RAW,
- iview->offset,
- iview->bo->size - iview->offset, 1);
+ iview->planes[vplane].isl.usage = 0;
}
- isl_surf_fill_image_param(&device->isl_dev,
- &iview->storage_image_param,
- &surface->isl, &iview->isl);
+ if (view_usage & VK_IMAGE_USAGE_SAMPLED_BIT ||
+ (view_usage & VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT &&
+ !(iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT))) {
+ iview->planes[vplane].optimal_sampler_surface_state.state = alloc_surface_state(device);
+ iview->planes[vplane].general_sampler_surface_state.state = alloc_surface_state(device);
+
+ enum isl_aux_usage general_aux_usage =
+ anv_layout_to_aux_usage(&device->info, image, 1UL << iaspect_bit,
+ VK_IMAGE_LAYOUT_GENERAL);
+ enum isl_aux_usage optimal_aux_usage =
+ anv_layout_to_aux_usage(&device->info, image, 1UL << iaspect_bit,
+ VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL);
+
+ anv_image_fill_surface_state(device, image, 1ULL << iaspect_bit,
+ &iview->planes[vplane].isl,
+ ISL_SURF_USAGE_TEXTURE_BIT,
+ optimal_aux_usage, NULL,
+ ANV_IMAGE_VIEW_STATE_TEXTURE_OPTIMAL,
+ &iview->planes[vplane].optimal_sampler_surface_state,
+ NULL);
+
+ anv_image_fill_surface_state(device, image, 1ULL << iaspect_bit,
+ &iview->planes[vplane].isl,
+ ISL_SURF_USAGE_TEXTURE_BIT,
+ general_aux_usage, NULL,
+ 0,
+ &iview->planes[vplane].general_sampler_surface_state,
+ NULL);
+ }
- anv_state_flush(device, iview->storage_surface_state);
- anv_state_flush(device, iview->writeonly_storage_surface_state);
- } else {
- iview->storage_surface_state.alloc_size = 0;
- iview->writeonly_storage_surface_state.alloc_size = 0;
+ /* NOTE: This one needs to go last since it may stomp isl_view.format */
+ if (view_usage & VK_IMAGE_USAGE_STORAGE_BIT) {
+ iview->planes[vplane].storage_surface_state.state = alloc_surface_state(device);
+ iview->planes[vplane].writeonly_storage_surface_state.state = alloc_surface_state(device);
+
+ anv_image_fill_surface_state(device, image, 1ULL << iaspect_bit,
+ &iview->planes[vplane].isl,
+ ISL_SURF_USAGE_STORAGE_BIT,
+ ISL_AUX_USAGE_NONE, NULL,
+ 0,
+ &iview->planes[vplane].storage_surface_state,
+ &iview->planes[vplane].storage_image_param);
+
+ anv_image_fill_surface_state(device, image, 1ULL << iaspect_bit,
+ &iview->planes[vplane].isl,
+ ISL_SURF_USAGE_STORAGE_BIT,
+ ISL_AUX_USAGE_NONE, NULL,
+ ANV_IMAGE_VIEW_STATE_STORAGE_WRITE_ONLY,
+ &iview->planes[vplane].writeonly_storage_surface_state,
+ NULL);
+ }
+
+ vplane++;
}
*pView = anv_image_view_to_handle(iview);
if (!iview)
return;
- if (iview->sampler_surface_state.alloc_size > 0) {
- anv_state_pool_free(&device->surface_state_pool,
- iview->sampler_surface_state);
- }
+ for (uint32_t plane = 0; plane < iview->n_planes; plane++) {
+ if (iview->planes[plane].optimal_sampler_surface_state.state.alloc_size > 0) {
+ anv_state_pool_free(&device->surface_state_pool,
+ iview->planes[plane].optimal_sampler_surface_state.state);
+ }
- if (iview->storage_surface_state.alloc_size > 0) {
- anv_state_pool_free(&device->surface_state_pool,
- iview->storage_surface_state);
- }
+ if (iview->planes[plane].general_sampler_surface_state.state.alloc_size > 0) {
+ anv_state_pool_free(&device->surface_state_pool,
+ iview->planes[plane].general_sampler_surface_state.state);
+ }
- if (iview->writeonly_storage_surface_state.alloc_size > 0) {
- anv_state_pool_free(&device->surface_state_pool,
- iview->writeonly_storage_surface_state);
+ if (iview->planes[plane].storage_surface_state.state.alloc_size > 0) {
+ anv_state_pool_free(&device->surface_state_pool,
+ iview->planes[plane].storage_surface_state.state);
+ }
+
+ if (iview->planes[plane].writeonly_storage_surface_state.state.alloc_size > 0) {
+ anv_state_pool_free(&device->surface_state_pool,
+ iview->planes[plane].writeonly_storage_surface_state.state);
+ }
}
vk_free2(&device->alloc, pAllocator, iview);
VK_IMAGE_ASPECT_COLOR_BIT,
VK_IMAGE_TILING_LINEAR);
const uint32_t format_bs = isl_format_get_layout(view->format)->bpb / 8;
- view->bo = buffer->bo;
- view->offset = buffer->offset + pCreateInfo->offset;
view->range = anv_buffer_get_range(buffer, pCreateInfo->offset,
pCreateInfo->range);
view->range = align_down_npot_u32(view->range, format_bs);
+ view->address = anv_address_add(buffer->address, pCreateInfo->offset);
+
if (buffer->usage & VK_BUFFER_USAGE_UNIFORM_TEXEL_BUFFER_BIT) {
view->surface_state = alloc_surface_state(device);
anv_fill_buffer_surface_state(device, view->surface_state,
view->format,
- view->offset, view->range, format_bs);
+ view->address, view->range, format_bs);
} else {
view->surface_state = (struct anv_state){ 0 };
}
anv_fill_buffer_surface_state(device, view->storage_surface_state,
storage_format,
- view->offset, view->range,
+ view->address, view->range,
(storage_format == ISL_FORMAT_RAW ? 1 :
isl_format_get_layout(storage_format)->bpb / 8));
/* Write-only accesses should use the original format. */
anv_fill_buffer_surface_state(device, view->writeonly_storage_surface_state,
view->format,
- view->offset, view->range,
+ view->address, view->range,
isl_format_get_layout(view->format)->bpb / 8);
isl_buffer_fill_image_param(&device->isl_dev,
anv_image_get_surface_for_aspect_mask(const struct anv_image *image,
VkImageAspectFlags aspect_mask)
{
+ VkImageAspectFlags sanitized_mask;
+
switch (aspect_mask) {
case VK_IMAGE_ASPECT_COLOR_BIT:
assert(image->aspects == VK_IMAGE_ASPECT_COLOR_BIT);
- return &image->color_surface;
+ sanitized_mask = VK_IMAGE_ASPECT_COLOR_BIT;
+ break;
case VK_IMAGE_ASPECT_DEPTH_BIT:
assert(image->aspects & VK_IMAGE_ASPECT_DEPTH_BIT);
- return &image->depth_surface;
+ sanitized_mask = VK_IMAGE_ASPECT_DEPTH_BIT;
+ break;
case VK_IMAGE_ASPECT_STENCIL_BIT:
assert(image->aspects & VK_IMAGE_ASPECT_STENCIL_BIT);
- return &image->stencil_surface;
+ sanitized_mask = VK_IMAGE_ASPECT_STENCIL_BIT;
+ break;
case VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT:
/* FINISHME: The Vulkan spec (git a511ba2) requires support for
* combined depth stencil formats. Specifically, it states:
* stencil surfaces from the underlying surface.
*/
if (image->aspects & VK_IMAGE_ASPECT_DEPTH_BIT) {
- return &image->depth_surface;
+ sanitized_mask = VK_IMAGE_ASPECT_DEPTH_BIT;
} else {
assert(image->aspects == VK_IMAGE_ASPECT_STENCIL_BIT);
- return &image->stencil_surface;
+ sanitized_mask = VK_IMAGE_ASPECT_STENCIL_BIT;
}
- default:
+ break;
+ case VK_IMAGE_ASPECT_PLANE_0_BIT:
+ assert((image->aspects & ~VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) == 0);
+ sanitized_mask = VK_IMAGE_ASPECT_PLANE_0_BIT;
+ break;
+ case VK_IMAGE_ASPECT_PLANE_1_BIT:
+ assert((image->aspects & ~VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) == 0);
+ sanitized_mask = VK_IMAGE_ASPECT_PLANE_1_BIT;
+ break;
+ case VK_IMAGE_ASPECT_PLANE_2_BIT:
+ assert((image->aspects & ~VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) == 0);
+ sanitized_mask = VK_IMAGE_ASPECT_PLANE_2_BIT;
+ break;
+ default:
unreachable("image does not have aspect");
return NULL;
}
+
+ uint32_t plane = anv_image_aspect_to_plane(image->aspects, sanitized_mask);
+ return &image->planes[plane].surface;
}
projects / mesa.git / blobdiff