winsys/amdgpu: avoid ioctl call when fence_wait is called without timeout
[mesa.git] / src / intel / vulkan / anv_meta_blit2d.c
index a7405e00810ad02028118b86150757503559062d..06e104329527e77b80bb78d08482a11fc060f045 100644 (file)
@@ -344,17 +344,6 @@ blit2d_bind_dst(struct anv_cmd_buffer *cmd_buffer,
          .height = height,
          .layers = 1
       }, &cmd_buffer->pool->alloc, &tmp->fb);
-
-
-   anv_CmdSetViewport(anv_cmd_buffer_to_handle(cmd_buffer), 0, 1,
-                      &(VkViewport) {
-                         .x = 0.0f,
-                         .y = 0.0f,
-                         .width = width,
-                         .height = height,
-                         .minDepth = 0.0f,
-                         .maxDepth = 1.0f,
-                      });
 }
 
 static void
@@ -377,8 +366,7 @@ void
 anv_meta_begin_blit2d(struct anv_cmd_buffer *cmd_buffer,
                       struct anv_meta_saved_state *save)
 {
-   anv_meta_save(save, cmd_buffer,
-                 (1 << VK_DYNAMIC_STATE_VIEWPORT));
+   anv_meta_save(save, cmd_buffer, 0);
 }
 
 static void
@@ -1022,9 +1010,7 @@ build_nir_w_tiled_fragment_shader(struct anv_device *device,
    discard->src[0] = nir_src_for_ssa(oob);
    nir_builder_instr_insert(&b, &discard->instr);
 
-   unsigned swiz[4] = { 0, 1, 0, 0 };
-   nir_ssa_def *tex_off =
-      nir_swizzle(&b, nir_load_var(&b, tex_off_in), swiz, 2, false);
+   nir_ssa_def *tex_off = nir_channels(&b, nir_load_var(&b, tex_off_in), 0x3);
    nir_ssa_def *tex_pos = nir_iadd(&b, nir_vec2(&b, x_W, y_W), tex_off);
    nir_ssa_def *tex_pitch = nir_channel(&b, nir_load_var(&b, tex_off_in), 2);
 
@@ -1202,8 +1188,6 @@ blit2d_init_pipeline(struct anv_device *device,
    const struct anv_graphics_pipeline_create_info anv_pipeline_info = {
       .color_attachment_count = -1,
       .use_repclear = false,
-      .disable_viewport = true,
-      .disable_scissor = true,
       .disable_vs = true,
       .use_rectlist = true
    };