nir: move data.image.access to data.access

[mesa.git] / src / intel / vulkan / anv_nir_apply_pipeline_layout.c

diff --git a/src/intel/vulkan/anv_nir_apply_pipeline_layout.c b/src/intel/vulkan/anv_nir_apply_pipeline_layout.c
index f37b672543b710784b177461bac4264bf78d111c..3fdc3520025977584fc1d97be7f522ca1c11cac8 100644 (file)
--- a/src/intel/vulkan/anv_nir_apply_pipeline_layout.c
+++ b/src/intel/vulkan/anv_nir_apply_pipeline_layout.c
@@ -752,7 +752,7 @@ lower_image_intrinsic(nir_intrinsic_instr *intrin,
       nir_ssa_def_rewrite_uses(&intrin->dest.ssa, nir_src_for_ssa(desc));
    } else if (binding_offset > MAX_BINDING_TABLE_SIZE) {
       const bool write_only =
-         (var->data.image.access & ACCESS_NON_READABLE) != 0;
+         (var->data.access & ACCESS_NON_READABLE) != 0;
       nir_ssa_def *desc =
          build_descriptor_load(deref, 0, 2, 32, state);
       nir_ssa_def *handle = nir_channel(b, desc, write_only ? 1 : 0);
@@ -1321,7 +1321,7 @@ anv_nir_apply_pipeline_layout(const struct anv_physical_device *pdevice,
 
          /* NOTE: This is a uint8_t so we really do need to != 0 here */
          pipe_binding[i].write_only =
-            (var->data.image.access & ACCESS_NON_READABLE) != 0;
+            (var->data.access & ACCESS_NON_READABLE) != 0;
       }
    }