anv: Emit cherryview SF state without including gen9_pack.h
[mesa.git] / src / intel / vulkan / anv_nir_apply_pipeline_layout.c
index e745bf661ee8f77daea7fffebc223418c5b17f73..8846c2e6c08e6fc3ceb857f72c68b759ab6ceedd 100644 (file)
@@ -29,6 +29,9 @@ struct apply_pipeline_layout_state {
    nir_shader *shader;
    nir_builder builder;
 
+   struct anv_pipeline_layout *layout;
+   bool add_bounds_checks;
+
    struct {
       BITSET_WORD *used;
       uint8_t *surface_offsets;
@@ -50,12 +53,11 @@ add_var_binding(struct apply_pipeline_layout_state *state, nir_variable *var)
    add_binding(state, var->data.descriptor_set, var->data.binding);
 }
 
-static bool
-get_used_bindings_block(nir_block *block, void *void_state)
+static void
+get_used_bindings_block(nir_block *block,
+                        struct apply_pipeline_layout_state *state)
 {
-   struct apply_pipeline_layout_state *state = void_state;
-
-   nir_foreach_instr_safe(block, instr) {
+   nir_foreach_instr_safe(instr, block) {
       switch (instr->type) {
       case nir_instr_type_intrinsic: {
          nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
@@ -97,8 +99,6 @@ get_used_bindings_block(nir_block *block, void *void_state)
          continue;
       }
    }
-
-   return true;
 }
 
 static void
@@ -113,17 +113,15 @@ lower_res_index_intrinsic(nir_intrinsic_instr *intrin,
    uint32_t binding = nir_intrinsic_binding(intrin);
 
    uint32_t surface_index = state->set[set].surface_offsets[binding];
+   uint32_t array_size =
+      state->layout->set[set].layout->binding[binding].array_size;
 
-   nir_const_value *const_block_idx =
-      nir_src_as_const_value(intrin->src[0]);
+   nir_ssa_def *block_index = nir_ssa_for_src(b, intrin->src[0], 1);
 
-   nir_ssa_def *block_index;
-   if (const_block_idx) {
-      block_index = nir_imm_int(b, surface_index + const_block_idx->u[0]);
-   } else {
-      block_index = nir_iadd(b, nir_imm_int(b, surface_index),
-                             nir_ssa_for_src(b, intrin->src[0], 1));
-   }
+   if (state->add_bounds_checks)
+      block_index = nir_umin(b, block_index, nir_imm_int(b, array_size - 1));
+
+   block_index = nir_iadd(b, nir_imm_int(b, surface_index), block_index);
 
    assert(intrin->dest.is_ssa);
    nir_ssa_def_rewrite_uses(&intrin->dest.ssa, nir_src_for_ssa(block_index));
@@ -132,16 +130,24 @@ lower_res_index_intrinsic(nir_intrinsic_instr *intrin,
 
 static void
 lower_tex_deref(nir_tex_instr *tex, nir_deref_var *deref,
-                unsigned *const_index, nir_tex_src_type src_type,
+                unsigned *const_index, unsigned array_size,
+                nir_tex_src_type src_type,
                 struct apply_pipeline_layout_state *state)
 {
+   nir_builder *b = &state->builder;
+
    if (deref->deref.child) {
       assert(deref->deref.child->deref_type == nir_deref_type_array);
       nir_deref_array *deref_array = nir_deref_as_array(deref->deref.child);
 
-      *const_index += deref_array->base_offset;
-
       if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
+         nir_ssa_def *index =
+            nir_iadd(b, nir_imm_int(b, deref_array->base_offset),
+                        nir_ssa_for_src(b, deref_array->indirect, 1));
+
+         if (state->add_bounds_checks)
+            index = nir_umin(b, index, nir_imm_int(b, array_size - 1));
+
          nir_tex_src *new_srcs = rzalloc_array(tex, nir_tex_src,
                                                tex->num_srcs + 1);
 
@@ -157,10 +163,11 @@ lower_tex_deref(nir_tex_instr *tex, nir_deref_var *deref,
           * first-class texture source.
           */
          tex->src[tex->num_srcs].src_type = src_type;
+         nir_instr_rewrite_src(&tex->instr, &tex->src[tex->num_srcs].src,
+                               nir_src_for_ssa(index));
          tex->num_srcs++;
-         assert(deref_array->indirect.is_ssa);
-         nir_instr_rewrite_src(&tex->instr, &tex->src[tex->num_srcs - 1].src,
-                               deref_array->indirect);
+      } else {
+         *const_index += MIN2(deref_array->base_offset, array_size - 1);
       }
    }
 }
@@ -185,17 +192,23 @@ lower_tex(nir_tex_instr *tex, struct apply_pipeline_layout_state *state)
    /* No one should have come by and lowered it already */
    assert(tex->texture);
 
+   state->builder.cursor = nir_before_instr(&tex->instr);
+
    unsigned set = tex->texture->var->data.descriptor_set;
    unsigned binding = tex->texture->var->data.binding;
+   unsigned array_size =
+      state->layout->set[set].layout->binding[binding].array_size;
    tex->texture_index = state->set[set].surface_offsets[binding];
-   lower_tex_deref(tex, tex->texture, &tex->texture_index,
+   lower_tex_deref(tex, tex->texture, &tex->texture_index, array_size,
                    nir_tex_src_texture_offset, state);
 
    if (tex->sampler) {
       unsigned set = tex->sampler->var->data.descriptor_set;
       unsigned binding = tex->sampler->var->data.binding;
+      unsigned array_size =
+         state->layout->set[set].layout->binding[binding].array_size;
       tex->sampler_index = state->set[set].sampler_offsets[binding];
-      lower_tex_deref(tex, tex->sampler, &tex->sampler_index,
+      lower_tex_deref(tex, tex->sampler, &tex->sampler_index, array_size,
                       nir_tex_src_sampler_offset, state);
    }
 
@@ -211,12 +224,11 @@ lower_tex(nir_tex_instr *tex, struct apply_pipeline_layout_state *state)
    tex->sampler = NULL;
 }
 
-static bool
-apply_pipeline_layout_block(nir_block *block, void *void_state)
+static void
+apply_pipeline_layout_block(nir_block *block,
+                            struct apply_pipeline_layout_state *state)
 {
-   struct apply_pipeline_layout_state *state = void_state;
-
-   nir_foreach_instr_safe(block, instr) {
+   nir_foreach_instr_safe(instr, block) {
       switch (instr->type) {
       case nir_instr_type_intrinsic: {
          nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
@@ -232,8 +244,6 @@ apply_pipeline_layout_block(nir_block *block, void *void_state)
          continue;
       }
    }
-
-   return true;
 }
 
 static void
@@ -253,12 +263,15 @@ setup_vec4_uniform_value(const union gl_constant_value **params,
 void
 anv_nir_apply_pipeline_layout(struct anv_pipeline *pipeline,
                               nir_shader *shader,
-                              struct brw_stage_prog_data *prog_data)
+                              struct brw_stage_prog_data *prog_data,
+                              struct anv_pipeline_bind_map *map)
 {
    struct anv_pipeline_layout *layout = pipeline->layout;
 
    struct apply_pipeline_layout_state state = {
       .shader = shader,
+      .layout = layout,
+      .add_bounds_checks = pipeline->device->robust_buffer_access,
    };
 
    void *mem_ctx = ralloc_context(NULL);
@@ -272,16 +285,13 @@ anv_nir_apply_pipeline_layout(struct anv_pipeline *pipeline,
       state.set[s].image_offsets = rzalloc_array(mem_ctx, uint8_t, count);
    }
 
-   nir_foreach_function(shader, function) {
-      if (function->impl)
-         nir_foreach_block(function->impl, get_used_bindings_block, &state);
-   }
+   nir_foreach_function(function, shader) {
+      if (!function->impl)
+         continue;
 
-   struct anv_pipeline_bind_map map = {
-      .surface_count = 0,
-      .sampler_count = 0,
-      .image_count = 0,
-   };
+      nir_foreach_block(block, function->impl)
+         get_used_bindings_block(block, &state);
+   }
 
    for (uint32_t set = 0; set < layout->num_sets; set++) {
       struct anv_descriptor_set_layout *set_layout = layout->set[set].layout;
@@ -290,21 +300,14 @@ anv_nir_apply_pipeline_layout(struct anv_pipeline *pipeline,
       BITSET_FOREACH_SET(b, _tmp, state.set[set].used,
                          set_layout->binding_count) {
          if (set_layout->binding[b].stage[shader->stage].surface_index >= 0)
-            map.surface_count += set_layout->binding[b].array_size;
+            map->surface_count += set_layout->binding[b].array_size;
          if (set_layout->binding[b].stage[shader->stage].sampler_index >= 0)
-            map.sampler_count += set_layout->binding[b].array_size;
+            map->sampler_count += set_layout->binding[b].array_size;
          if (set_layout->binding[b].stage[shader->stage].image_index >= 0)
-            map.image_count += set_layout->binding[b].array_size;
+            map->image_count += set_layout->binding[b].array_size;
       }
    }
 
-   map.surface_to_descriptor =
-      malloc(map.surface_count * sizeof(struct anv_pipeline_binding));
-   map.sampler_to_descriptor =
-      malloc(map.sampler_count * sizeof(struct anv_pipeline_binding));
-
-   pipeline->bindings[shader->stage] = map;
-
    unsigned surface = 0;
    unsigned sampler = 0;
    unsigned image = 0;
@@ -315,13 +318,13 @@ anv_nir_apply_pipeline_layout(struct anv_pipeline *pipeline,
       BITSET_FOREACH_SET(b, _tmp, state.set[set].used,
                          set_layout->binding_count) {
          unsigned array_size = set_layout->binding[b].array_size;
-         unsigned set_offset = set_layout->binding[b].descriptor_index;
 
          if (set_layout->binding[b].stage[shader->stage].surface_index >= 0) {
             state.set[set].surface_offsets[b] = surface;
             for (unsigned i = 0; i < array_size; i++) {
-               map.surface_to_descriptor[surface + i].set = set;
-               map.surface_to_descriptor[surface + i].offset = set_offset + i;
+               map->surface_to_descriptor[surface + i].set = set;
+               map->surface_to_descriptor[surface + i].binding = b;
+               map->surface_to_descriptor[surface + i].index = i;
             }
             surface += array_size;
          }
@@ -329,8 +332,9 @@ anv_nir_apply_pipeline_layout(struct anv_pipeline *pipeline,
          if (set_layout->binding[b].stage[shader->stage].sampler_index >= 0) {
             state.set[set].sampler_offsets[b] = sampler;
             for (unsigned i = 0; i < array_size; i++) {
-               map.sampler_to_descriptor[sampler + i].set = set;
-               map.sampler_to_descriptor[sampler + i].offset = set_offset + i;
+               map->sampler_to_descriptor[sampler + i].set = set;
+               map->sampler_to_descriptor[sampler + i].binding = b;
+               map->sampler_to_descriptor[sampler + i].index = i;
             }
             sampler += array_size;
          }
@@ -342,17 +346,46 @@ anv_nir_apply_pipeline_layout(struct anv_pipeline *pipeline,
       }
    }
 
-   nir_foreach_function(shader, function) {
-      if (function->impl) {
-         nir_builder_init(&state.builder, function->impl);
-         nir_foreach_block(function->impl, apply_pipeline_layout_block, &state);
-         nir_metadata_preserve(function->impl, nir_metadata_block_index |
-                                               nir_metadata_dominance);
+   nir_foreach_variable(var, &shader->uniforms) {
+      if (!glsl_type_is_image(var->interface_type))
+         continue;
+
+      enum glsl_sampler_dim dim = glsl_get_sampler_dim(var->interface_type);
+      if (dim != GLSL_SAMPLER_DIM_SUBPASS &&
+          dim != GLSL_SAMPLER_DIM_SUBPASS_MS)
+         continue;
+
+      const uint32_t set = var->data.descriptor_set;
+      const uint32_t binding = var->data.binding;
+      const uint32_t array_size =
+         layout->set[set].layout->binding[binding].array_size;
+
+      if (!BITSET_TEST(state.set[set].used, binding))
+         continue;
+
+      struct anv_pipeline_binding *pipe_binding =
+         &map->surface_to_descriptor[state.set[set].surface_offsets[binding]];
+      for (unsigned i = 0; i < array_size; i++) {
+         assert(pipe_binding[i].set == set);
+         assert(pipe_binding[i].binding == binding);
+         assert(pipe_binding[i].index == i);
+         pipe_binding[i].input_attachment_index = var->data.index + i;
       }
    }
 
-   if (map.image_count > 0) {
-      assert(map.image_count <= MAX_IMAGES);
+   nir_foreach_function(function, shader) {
+      if (!function->impl)
+         continue;
+
+      nir_builder_init(&state.builder, function->impl);
+      nir_foreach_block(block, function->impl)
+         apply_pipeline_layout_block(block, &state);
+      nir_metadata_preserve(function->impl, nir_metadata_block_index |
+                                            nir_metadata_dominance);
+   }
+
+   if (map->image_count > 0) {
+      assert(map->image_count <= MAX_IMAGES);
       nir_foreach_variable(var, &shader->uniforms) {
          if (glsl_type_is_image(var->type) ||
              (glsl_type_is_array(var->type) &&
@@ -374,7 +407,7 @@ anv_nir_apply_pipeline_layout(struct anv_pipeline *pipeline,
       const gl_constant_value **param =
          prog_data->param + (shader->num_uniforms / 4);
       const struct brw_image_param *image_param = null_data->images;
-      for (uint32_t i = 0; i < map.image_count; i++) {
+      for (uint32_t i = 0; i < map->image_count; i++) {
          setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET,
             (const union gl_constant_value *)&image_param->surface_idx, 1);
          setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_OFFSET_OFFSET,
@@ -392,7 +425,7 @@ anv_nir_apply_pipeline_layout(struct anv_pipeline *pipeline,
          image_param ++;
       }
 
-      shader->num_uniforms += map.image_count * BRW_IMAGE_PARAM_SIZE * 4;
+      shader->num_uniforms += map->image_count * BRW_IMAGE_PARAM_SIZE * 4;
    }
 
    ralloc_free(mem_ctx);