gallium: add separate PIPE_CAP_INT64_DIVMOD

[mesa.git] / src / intel / vulkan / anv_nir_apply_pipeline_layout.c

diff --git a/src/intel/vulkan/anv_nir_apply_pipeline_layout.c b/src/intel/vulkan/anv_nir_apply_pipeline_layout.c
index 64812693973e94a8d4fc07277869fcadad8b1b41..8846c2e6c08e6fc3ceb857f72c68b759ab6ceedd 100644 (file)
--- a/src/intel/vulkan/anv_nir_apply_pipeline_layout.c
+++ b/src/intel/vulkan/anv_nir_apply_pipeline_layout.c
@@ -318,13 +318,13 @@ anv_nir_apply_pipeline_layout(struct anv_pipeline *pipeline,
       BITSET_FOREACH_SET(b, _tmp, state.set[set].used,
                          set_layout->binding_count) {
          unsigned array_size = set_layout->binding[b].array_size;
-         unsigned set_offset = set_layout->binding[b].descriptor_index;
 
          if (set_layout->binding[b].stage[shader->stage].surface_index >= 0) {
             state.set[set].surface_offsets[b] = surface;
             for (unsigned i = 0; i < array_size; i++) {
                map->surface_to_descriptor[surface + i].set = set;
-               map->surface_to_descriptor[surface + i].offset = set_offset + i;
+               map->surface_to_descriptor[surface + i].binding = b;
+               map->surface_to_descriptor[surface + i].index = i;
             }
             surface += array_size;
          }
@@ -333,7 +333,8 @@ anv_nir_apply_pipeline_layout(struct anv_pipeline *pipeline,
             state.set[set].sampler_offsets[b] = sampler;
             for (unsigned i = 0; i < array_size; i++) {
                map->sampler_to_descriptor[sampler + i].set = set;
-               map->sampler_to_descriptor[sampler + i].offset = set_offset + i;
+               map->sampler_to_descriptor[sampler + i].binding = b;
+               map->sampler_to_descriptor[sampler + i].index = i;
             }
             sampler += array_size;
          }
@@ -345,6 +346,33 @@ anv_nir_apply_pipeline_layout(struct anv_pipeline *pipeline,
       }
    }
 
+   nir_foreach_variable(var, &shader->uniforms) {
+      if (!glsl_type_is_image(var->interface_type))
+         continue;
+
+      enum glsl_sampler_dim dim = glsl_get_sampler_dim(var->interface_type);
+      if (dim != GLSL_SAMPLER_DIM_SUBPASS &&
+          dim != GLSL_SAMPLER_DIM_SUBPASS_MS)
+         continue;
+
+      const uint32_t set = var->data.descriptor_set;
+      const uint32_t binding = var->data.binding;
+      const uint32_t array_size =
+         layout->set[set].layout->binding[binding].array_size;
+
+      if (!BITSET_TEST(state.set[set].used, binding))
+         continue;
+
+      struct anv_pipeline_binding *pipe_binding =
+         &map->surface_to_descriptor[state.set[set].surface_offsets[binding]];
+      for (unsigned i = 0; i < array_size; i++) {
+         assert(pipe_binding[i].set == set);
+         assert(pipe_binding[i].binding == binding);
+         assert(pipe_binding[i].index == i);
+         pipe_binding[i].input_attachment_index = var->data.index + i;
+      }
+   }
+
    nir_foreach_function(function, shader) {
       if (!function->impl)
          continue;