#include "anv_nir.h"
#include "program/prog_parameter.h"
#include "nir/nir_builder.h"
+#include "compiler/brw_nir.h"
struct apply_pipeline_layout_state {
+ const struct anv_physical_device *pdevice;
+
nir_shader *shader;
nir_builder builder;
+ struct anv_pipeline_layout *layout;
+ bool add_bounds_checks;
+
+ unsigned first_image_uniform;
+
+ bool uses_constants;
+ uint8_t constants_offset;
struct {
+ bool desc_buffer_used;
+ uint8_t desc_offset;
+
BITSET_WORD *used;
uint8_t *surface_offsets;
uint8_t *sampler_offsets;
add_binding(struct apply_pipeline_layout_state *state,
uint32_t set, uint32_t binding)
{
+ const struct anv_descriptor_set_binding_layout *bind_layout =
+ &state->layout->set[set].layout->binding[binding];
+
BITSET_SET(state->set[set].used, binding);
+
+ /* Only flag the descriptor buffer as used if there's actually data for
+ * this binding. This lets us be lazy and call this function constantly
+ * without worrying about unnecessarily enabling the buffer.
+ */
+ if (anv_descriptor_size(bind_layout))
+ state->set[set].desc_buffer_used = true;
}
static void
-add_var_binding(struct apply_pipeline_layout_state *state, nir_variable *var)
+add_deref_src_binding(struct apply_pipeline_layout_state *state, nir_src src)
{
+ nir_deref_instr *deref = nir_src_as_deref(src);
+ nir_variable *var = nir_deref_instr_get_variable(deref);
add_binding(state, var->data.descriptor_set, var->data.binding);
}
-static bool
-get_used_bindings_block(nir_block *block, void *void_state)
+static void
+add_tex_src_binding(struct apply_pipeline_layout_state *state,
+ nir_tex_instr *tex, nir_tex_src_type deref_src_type)
{
- struct apply_pipeline_layout_state *state = void_state;
+ int deref_src_idx = nir_tex_instr_src_index(tex, deref_src_type);
+ if (deref_src_idx < 0)
+ return;
- nir_foreach_instr_safe(block, instr) {
+ add_deref_src_binding(state, tex->src[deref_src_idx].src);
+}
+
+static void
+get_used_bindings_block(nir_block *block,
+ struct apply_pipeline_layout_state *state)
+{
+ nir_foreach_instr_safe(instr, block) {
switch (instr->type) {
case nir_instr_type_intrinsic: {
nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
nir_intrinsic_binding(intrin));
break;
- case nir_intrinsic_image_load:
- case nir_intrinsic_image_store:
- case nir_intrinsic_image_atomic_add:
- case nir_intrinsic_image_atomic_min:
- case nir_intrinsic_image_atomic_max:
- case nir_intrinsic_image_atomic_and:
- case nir_intrinsic_image_atomic_or:
- case nir_intrinsic_image_atomic_xor:
- case nir_intrinsic_image_atomic_exchange:
- case nir_intrinsic_image_atomic_comp_swap:
- case nir_intrinsic_image_size:
- case nir_intrinsic_image_samples:
- add_var_binding(state, intrin->variables[0]->var);
+ case nir_intrinsic_image_deref_load:
+ case nir_intrinsic_image_deref_store:
+ case nir_intrinsic_image_deref_atomic_add:
+ case nir_intrinsic_image_deref_atomic_min:
+ case nir_intrinsic_image_deref_atomic_max:
+ case nir_intrinsic_image_deref_atomic_and:
+ case nir_intrinsic_image_deref_atomic_or:
+ case nir_intrinsic_image_deref_atomic_xor:
+ case nir_intrinsic_image_deref_atomic_exchange:
+ case nir_intrinsic_image_deref_atomic_comp_swap:
+ case nir_intrinsic_image_deref_size:
+ case nir_intrinsic_image_deref_samples:
+ case nir_intrinsic_image_deref_load_param_intel:
+ case nir_intrinsic_image_deref_load_raw_intel:
+ case nir_intrinsic_image_deref_store_raw_intel:
+ add_deref_src_binding(state, intrin->src[0]);
+ break;
+
+ case nir_intrinsic_load_constant:
+ state->uses_constants = true;
break;
default:
}
case nir_instr_type_tex: {
nir_tex_instr *tex = nir_instr_as_tex(instr);
- assert(tex->texture);
- add_var_binding(state, tex->texture->var);
- if (tex->sampler)
- add_var_binding(state, tex->sampler->var);
+ add_tex_src_binding(state, tex, nir_tex_src_texture_deref);
+ add_tex_src_binding(state, tex, nir_tex_src_sampler_deref);
break;
}
default:
continue;
}
}
-
- return true;
}
static void
uint32_t set = nir_intrinsic_desc_set(intrin);
uint32_t binding = nir_intrinsic_binding(intrin);
+ const struct anv_descriptor_set_binding_layout *bind_layout =
+ &state->layout->set[set].layout->binding[binding];
+
uint32_t surface_index = state->set[set].surface_offsets[binding];
+ uint32_t array_size = bind_layout->array_size;
+
+ nir_ssa_def *array_index = nir_ssa_for_src(b, intrin->src[0], 1);
+ if (nir_src_is_const(intrin->src[0]) || state->add_bounds_checks)
+ array_index = nir_umin(b, array_index, nir_imm_int(b, array_size - 1));
+
+ nir_ssa_def *index;
+ if (bind_layout->data & ANV_DESCRIPTOR_INLINE_UNIFORM) {
+ /* This is an inline uniform block. Just reference the descriptor set
+ * and use the descriptor offset as the base.
+ */
+ index = nir_imm_ivec2(b, state->set[set].desc_offset,
+ bind_layout->descriptor_offset);
+ } else {
+ /* We're using nir_address_format_32bit_index_offset */
+ index = nir_vec2(b, nir_iadd_imm(b, array_index, surface_index),
+ nir_imm_int(b, 0));
+ }
- nir_const_value *const_block_idx =
- nir_src_as_const_value(intrin->src[0]);
+ assert(intrin->dest.is_ssa);
+ nir_ssa_def_rewrite_uses(&intrin->dest.ssa, nir_src_for_ssa(index));
+ nir_instr_remove(&intrin->instr);
+}
+
+static void
+lower_res_reindex_intrinsic(nir_intrinsic_instr *intrin,
+ struct apply_pipeline_layout_state *state)
+{
+ nir_builder *b = &state->builder;
+
+ b->cursor = nir_before_instr(&intrin->instr);
- nir_ssa_def *block_index;
- if (const_block_idx) {
- block_index = nir_imm_int(b, surface_index + const_block_idx->u32[0]);
+ /* For us, the resource indices are just indices into the binding table and
+ * array elements are sequential. A resource_reindex just turns into an
+ * add of the two indices.
+ */
+ assert(intrin->src[0].is_ssa && intrin->src[1].is_ssa);
+ nir_ssa_def *old_index = intrin->src[0].ssa;
+ nir_ssa_def *offset = intrin->src[1].ssa;
+
+ nir_ssa_def *new_index =
+ nir_vec2(b, nir_iadd(b, nir_channel(b, old_index, 0), offset),
+ nir_channel(b, old_index, 1));
+
+ assert(intrin->dest.is_ssa);
+ nir_ssa_def_rewrite_uses(&intrin->dest.ssa, nir_src_for_ssa(new_index));
+ nir_instr_remove(&intrin->instr);
+}
+
+static void
+lower_load_vulkan_descriptor(nir_intrinsic_instr *intrin,
+ struct apply_pipeline_layout_state *state)
+{
+ nir_builder *b = &state->builder;
+
+ b->cursor = nir_before_instr(&intrin->instr);
+
+ /* We follow the nir_address_format_32bit_index_offset model */
+ assert(intrin->src[0].is_ssa);
+ nir_ssa_def *index = intrin->src[0].ssa;
+
+ assert(intrin->dest.is_ssa);
+ nir_ssa_def_rewrite_uses(&intrin->dest.ssa, nir_src_for_ssa(index));
+ nir_instr_remove(&intrin->instr);
+}
+
+static void
+lower_get_buffer_size(nir_intrinsic_instr *intrin,
+ struct apply_pipeline_layout_state *state)
+{
+ nir_builder *b = &state->builder;
+
+ b->cursor = nir_before_instr(&intrin->instr);
+
+ assert(intrin->src[0].is_ssa);
+ nir_ssa_def *index = intrin->src[0].ssa;
+
+ /* We're following the nir_address_format_32bit_index_offset model so the
+ * binding table index is the first component of the address. The
+ * back-end wants a scalar binding table index source.
+ */
+ nir_instr_rewrite_src(&intrin->instr, &intrin->src[0],
+ nir_src_for_ssa(nir_channel(b, index, 0)));
+}
+
+static void
+lower_image_intrinsic(nir_intrinsic_instr *intrin,
+ struct apply_pipeline_layout_state *state)
+{
+ nir_deref_instr *deref = nir_src_as_deref(intrin->src[0]);
+ nir_variable *var = nir_deref_instr_get_variable(deref);
+
+ unsigned set = var->data.descriptor_set;
+ unsigned binding = var->data.binding;
+ unsigned array_size =
+ state->layout->set[set].layout->binding[binding].array_size;
+
+ nir_builder *b = &state->builder;
+ b->cursor = nir_before_instr(&intrin->instr);
+
+ nir_ssa_def *index = NULL;
+ if (deref->deref_type != nir_deref_type_var) {
+ assert(deref->deref_type == nir_deref_type_array);
+ index = nir_ssa_for_src(b, deref->arr.index, 1);
+ if (state->add_bounds_checks)
+ index = nir_umin(b, index, nir_imm_int(b, array_size - 1));
} else {
- block_index = nir_iadd(b, nir_imm_int(b, surface_index),
- nir_ssa_for_src(b, intrin->src[0], 1));
+ index = nir_imm_int(b, 0);
}
- assert(intrin->dest.is_ssa);
- nir_ssa_def_rewrite_uses(&intrin->dest.ssa, nir_src_for_ssa(block_index));
+ if (intrin->intrinsic == nir_intrinsic_image_deref_load_param_intel) {
+ b->cursor = nir_instr_remove(&intrin->instr);
+
+ nir_intrinsic_instr *load =
+ nir_intrinsic_instr_create(b->shader, nir_intrinsic_load_uniform);
+
+ nir_intrinsic_set_base(load, state->first_image_uniform +
+ state->set[set].image_offsets[binding] *
+ BRW_IMAGE_PARAM_SIZE * 4);
+ nir_intrinsic_set_range(load, array_size * BRW_IMAGE_PARAM_SIZE * 4);
+
+ const unsigned param = nir_intrinsic_base(intrin);
+ nir_ssa_def *offset =
+ nir_imul(b, index, nir_imm_int(b, BRW_IMAGE_PARAM_SIZE * 4));
+ offset = nir_iadd(b, offset, nir_imm_int(b, param * 16));
+ load->src[0] = nir_src_for_ssa(offset);
+
+ load->num_components = intrin->dest.ssa.num_components;
+ nir_ssa_dest_init(&load->instr, &load->dest,
+ intrin->dest.ssa.num_components,
+ intrin->dest.ssa.bit_size, NULL);
+ nir_builder_instr_insert(b, &load->instr);
+
+ nir_ssa_def_rewrite_uses(&intrin->dest.ssa,
+ nir_src_for_ssa(&load->dest.ssa));
+ } else {
+ unsigned binding_offset = state->set[set].surface_offsets[binding];
+ index = nir_iadd(b, index, nir_imm_int(b, binding_offset));
+ brw_nir_rewrite_image_intrinsic(intrin, index);
+ }
+}
+
+static void
+lower_load_constant(nir_intrinsic_instr *intrin,
+ struct apply_pipeline_layout_state *state)
+{
+ nir_builder *b = &state->builder;
+
+ b->cursor = nir_before_instr(&intrin->instr);
+
+ nir_ssa_def *index = nir_imm_int(b, state->constants_offset);
+ nir_ssa_def *offset = nir_iadd(b, nir_ssa_for_src(b, intrin->src[0], 1),
+ nir_imm_int(b, nir_intrinsic_base(intrin)));
+
+ nir_intrinsic_instr *load_ubo =
+ nir_intrinsic_instr_create(b->shader, nir_intrinsic_load_ubo);
+ load_ubo->num_components = intrin->num_components;
+ load_ubo->src[0] = nir_src_for_ssa(index);
+ load_ubo->src[1] = nir_src_for_ssa(offset);
+ nir_ssa_dest_init(&load_ubo->instr, &load_ubo->dest,
+ intrin->dest.ssa.num_components,
+ intrin->dest.ssa.bit_size, NULL);
+ nir_builder_instr_insert(b, &load_ubo->instr);
+
+ nir_ssa_def_rewrite_uses(&intrin->dest.ssa,
+ nir_src_for_ssa(&load_ubo->dest.ssa));
nir_instr_remove(&intrin->instr);
}
static void
-lower_tex_deref(nir_tex_instr *tex, nir_deref_var *deref,
- unsigned *const_index, nir_tex_src_type src_type,
+lower_tex_deref(nir_tex_instr *tex, nir_tex_src_type deref_src_type,
+ unsigned *base_index,
struct apply_pipeline_layout_state *state)
{
- if (deref->deref.child) {
- assert(deref->deref.child->deref_type == nir_deref_type_array);
- nir_deref_array *deref_array = nir_deref_as_array(deref->deref.child);
-
- *const_index += deref_array->base_offset;
+ int deref_src_idx = nir_tex_instr_src_index(tex, deref_src_type);
+ if (deref_src_idx < 0)
+ return;
- if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
- nir_tex_src *new_srcs = rzalloc_array(tex, nir_tex_src,
- tex->num_srcs + 1);
+ nir_deref_instr *deref = nir_src_as_deref(tex->src[deref_src_idx].src);
+ nir_variable *var = nir_deref_instr_get_variable(deref);
- for (unsigned i = 0; i < tex->num_srcs; i++) {
- new_srcs[i].src_type = tex->src[i].src_type;
- nir_instr_move_src(&tex->instr, &new_srcs[i].src, &tex->src[i].src);
- }
+ unsigned set = var->data.descriptor_set;
+ unsigned binding = var->data.binding;
+ unsigned array_size =
+ state->layout->set[set].layout->binding[binding].array_size;
- ralloc_free(tex->src);
- tex->src = new_srcs;
+ nir_tex_src_type offset_src_type;
+ if (deref_src_type == nir_tex_src_texture_deref) {
+ offset_src_type = nir_tex_src_texture_offset;
+ *base_index = state->set[set].surface_offsets[binding];
+ } else {
+ assert(deref_src_type == nir_tex_src_sampler_deref);
+ offset_src_type = nir_tex_src_sampler_offset;
+ *base_index = state->set[set].sampler_offsets[binding];
+ }
- /* Now we can go ahead and move the source over to being a
- * first-class texture source.
+ nir_ssa_def *index = NULL;
+ if (deref->deref_type != nir_deref_type_var) {
+ assert(deref->deref_type == nir_deref_type_array);
+
+ if (nir_src_is_const(deref->arr.index)) {
+ unsigned arr_index = nir_src_as_uint(deref->arr.index);
+ *base_index += MIN2(arr_index, array_size - 1);
+ } else {
+ nir_builder *b = &state->builder;
+
+ /* From VK_KHR_sampler_ycbcr_conversion:
+ *
+ * If sampler Y’CBCR conversion is enabled, the combined image
+ * sampler must be indexed only by constant integral expressions when
+ * aggregated into arrays in shader code, irrespective of the
+ * shaderSampledImageArrayDynamicIndexing feature.
*/
- tex->src[tex->num_srcs].src_type = src_type;
- tex->num_srcs++;
- assert(deref_array->indirect.is_ssa);
- nir_instr_rewrite_src(&tex->instr, &tex->src[tex->num_srcs - 1].src,
- deref_array->indirect);
+ assert(nir_tex_instr_src_index(tex, nir_tex_src_plane) == -1);
+
+ index = nir_ssa_for_src(b, deref->arr.index, 1);
+
+ if (state->add_bounds_checks)
+ index = nir_umin(b, index, nir_imm_int(b, array_size - 1));
}
}
+
+ if (index) {
+ nir_instr_rewrite_src(&tex->instr, &tex->src[deref_src_idx].src,
+ nir_src_for_ssa(index));
+ tex->src[deref_src_idx].src_type = offset_src_type;
+ } else {
+ nir_tex_instr_remove_src(tex, deref_src_idx);
+ }
}
-static void
-cleanup_tex_deref(nir_tex_instr *tex, nir_deref_var *deref)
+static uint32_t
+tex_instr_get_and_remove_plane_src(nir_tex_instr *tex)
{
- if (deref->deref.child == NULL)
- return;
+ int plane_src_idx = nir_tex_instr_src_index(tex, nir_tex_src_plane);
+ if (plane_src_idx < 0)
+ return 0;
- nir_deref_array *deref_array = nir_deref_as_array(deref->deref.child);
+ unsigned plane = nir_src_as_uint(tex->src[plane_src_idx].src);
- if (deref_array->deref_array_type != nir_deref_array_type_indirect)
- return;
+ nir_tex_instr_remove_src(tex, plane_src_idx);
- nir_instr_rewrite_src(&tex->instr, &deref_array->indirect, NIR_SRC_INIT);
+ return plane;
}
static void
lower_tex(nir_tex_instr *tex, struct apply_pipeline_layout_state *state)
{
- /* No one should have come by and lowered it already */
- assert(tex->texture);
-
- unsigned set = tex->texture->var->data.descriptor_set;
- unsigned binding = tex->texture->var->data.binding;
- tex->texture_index = state->set[set].surface_offsets[binding];
- lower_tex_deref(tex, tex->texture, &tex->texture_index,
- nir_tex_src_texture_offset, state);
-
- if (tex->sampler) {
- unsigned set = tex->sampler->var->data.descriptor_set;
- unsigned binding = tex->sampler->var->data.binding;
- tex->sampler_index = state->set[set].sampler_offsets[binding];
- lower_tex_deref(tex, tex->sampler, &tex->sampler_index,
- nir_tex_src_sampler_offset, state);
- }
+ state->builder.cursor = nir_before_instr(&tex->instr);
+
+ unsigned plane = tex_instr_get_and_remove_plane_src(tex);
+
+ lower_tex_deref(tex, nir_tex_src_texture_deref,
+ &tex->texture_index, state);
+ tex->texture_index += plane;
+
+ lower_tex_deref(tex, nir_tex_src_sampler_deref,
+ &tex->sampler_index, state);
+ tex->sampler_index += plane;
/* The backend only ever uses this to mark used surfaces. We don't care
* about that little optimization so it just needs to be non-zero.
*/
tex->texture_array_size = 1;
-
- cleanup_tex_deref(tex, tex->texture);
- if (tex->sampler)
- cleanup_tex_deref(tex, tex->sampler);
- tex->texture = NULL;
- tex->sampler = NULL;
}
-static bool
-apply_pipeline_layout_block(nir_block *block, void *void_state)
+static void
+apply_pipeline_layout_block(nir_block *block,
+ struct apply_pipeline_layout_state *state)
{
- struct apply_pipeline_layout_state *state = void_state;
-
- nir_foreach_instr_safe(block, instr) {
+ nir_foreach_instr_safe(instr, block) {
switch (instr->type) {
case nir_instr_type_intrinsic: {
nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
- if (intrin->intrinsic == nir_intrinsic_vulkan_resource_index) {
+ switch (intrin->intrinsic) {
+ case nir_intrinsic_vulkan_resource_index:
lower_res_index_intrinsic(intrin, state);
+ break;
+ case nir_intrinsic_vulkan_resource_reindex:
+ lower_res_reindex_intrinsic(intrin, state);
+ break;
+ case nir_intrinsic_load_vulkan_descriptor:
+ lower_load_vulkan_descriptor(intrin, state);
+ break;
+ case nir_intrinsic_get_buffer_size:
+ lower_get_buffer_size(intrin, state);
+ break;
+ case nir_intrinsic_image_deref_load:
+ case nir_intrinsic_image_deref_store:
+ case nir_intrinsic_image_deref_atomic_add:
+ case nir_intrinsic_image_deref_atomic_min:
+ case nir_intrinsic_image_deref_atomic_max:
+ case nir_intrinsic_image_deref_atomic_and:
+ case nir_intrinsic_image_deref_atomic_or:
+ case nir_intrinsic_image_deref_atomic_xor:
+ case nir_intrinsic_image_deref_atomic_exchange:
+ case nir_intrinsic_image_deref_atomic_comp_swap:
+ case nir_intrinsic_image_deref_size:
+ case nir_intrinsic_image_deref_samples:
+ case nir_intrinsic_image_deref_load_param_intel:
+ case nir_intrinsic_image_deref_load_raw_intel:
+ case nir_intrinsic_image_deref_store_raw_intel:
+ lower_image_intrinsic(intrin, state);
+ break;
+ case nir_intrinsic_load_constant:
+ lower_load_constant(intrin, state);
+ break;
+ default:
+ break;
}
break;
}
continue;
}
}
-
- return true;
}
static void
-setup_vec4_uniform_value(const union gl_constant_value **params,
- const union gl_constant_value *values,
- unsigned n)
+setup_vec4_uniform_value(uint32_t *params, uint32_t offset, unsigned n)
{
- static const gl_constant_value zero = { 0 };
-
for (unsigned i = 0; i < n; ++i)
- params[i] = &values[i];
+ params[i] = ANV_PARAM_PUSH(offset + i * sizeof(uint32_t));
for (unsigned i = n; i < 4; ++i)
- params[i] = &zero;
+ params[i] = BRW_PARAM_BUILTIN_ZERO;
}
void
-anv_nir_apply_pipeline_layout(struct anv_pipeline *pipeline,
+anv_nir_apply_pipeline_layout(const struct anv_physical_device *pdevice,
+ bool robust_buffer_access,
+ struct anv_pipeline_layout *layout,
nir_shader *shader,
struct brw_stage_prog_data *prog_data,
struct anv_pipeline_bind_map *map)
{
- struct anv_pipeline_layout *layout = pipeline->layout;
-
struct apply_pipeline_layout_state state = {
+ .pdevice = pdevice,
.shader = shader,
+ .layout = layout,
+ .add_bounds_checks = robust_buffer_access,
};
void *mem_ctx = ralloc_context(NULL);
state.set[s].image_offsets = rzalloc_array(mem_ctx, uint8_t, count);
}
- nir_foreach_function(shader, function) {
- if (function->impl)
- nir_foreach_block(function->impl, get_used_bindings_block, &state);
- }
+ nir_foreach_function(function, shader) {
+ if (!function->impl)
+ continue;
- for (uint32_t set = 0; set < layout->num_sets; set++) {
- struct anv_descriptor_set_layout *set_layout = layout->set[set].layout;
+ nir_foreach_block(block, function->impl)
+ get_used_bindings_block(block, &state);
+ }
- BITSET_WORD b, _tmp;
- BITSET_FOREACH_SET(b, _tmp, state.set[set].used,
- set_layout->binding_count) {
- if (set_layout->binding[b].stage[shader->stage].surface_index >= 0)
- map->surface_count += set_layout->binding[b].array_size;
- if (set_layout->binding[b].stage[shader->stage].sampler_index >= 0)
- map->sampler_count += set_layout->binding[b].array_size;
- if (set_layout->binding[b].stage[shader->stage].image_index >= 0)
- map->image_count += set_layout->binding[b].array_size;
+ for (unsigned s = 0; s < layout->num_sets; s++) {
+ if (state.set[s].desc_buffer_used) {
+ map->surface_to_descriptor[map->surface_count] =
+ (struct anv_pipeline_binding) {
+ .set = ANV_DESCRIPTOR_SET_DESCRIPTORS,
+ .binding = s,
+ };
+ state.set[s].desc_offset = map->surface_count;
+ map->surface_count++;
}
}
- unsigned surface = 0;
- unsigned sampler = 0;
- unsigned image = 0;
+ if (state.uses_constants) {
+ state.constants_offset = map->surface_count;
+ map->surface_to_descriptor[map->surface_count].set =
+ ANV_DESCRIPTOR_SET_SHADER_CONSTANTS;
+ map->surface_count++;
+ }
+
for (uint32_t set = 0; set < layout->num_sets; set++) {
struct anv_descriptor_set_layout *set_layout = layout->set[set].layout;
BITSET_WORD b, _tmp;
BITSET_FOREACH_SET(b, _tmp, state.set[set].used,
set_layout->binding_count) {
- unsigned array_size = set_layout->binding[b].array_size;
- unsigned set_offset = set_layout->binding[b].descriptor_index;
-
- if (set_layout->binding[b].stage[shader->stage].surface_index >= 0) {
- state.set[set].surface_offsets[b] = surface;
- for (unsigned i = 0; i < array_size; i++) {
- map->surface_to_descriptor[surface + i].set = set;
- map->surface_to_descriptor[surface + i].offset = set_offset + i;
+ struct anv_descriptor_set_binding_layout *binding =
+ &set_layout->binding[b];
+
+ if (binding->array_size == 0)
+ continue;
+
+ if (binding->data & ANV_DESCRIPTOR_SURFACE_STATE) {
+ state.set[set].surface_offsets[b] = map->surface_count;
+ struct anv_sampler **samplers = binding->immutable_samplers;
+ for (unsigned i = 0; i < binding->array_size; i++) {
+ uint8_t planes = samplers ? samplers[i]->n_planes : 1;
+ for (uint8_t p = 0; p < planes; p++) {
+ map->surface_to_descriptor[map->surface_count++] =
+ (struct anv_pipeline_binding) {
+ .set = set,
+ .binding = b,
+ .index = i,
+ .plane = p,
+ };
+ }
}
- surface += array_size;
}
- if (set_layout->binding[b].stage[shader->stage].sampler_index >= 0) {
- state.set[set].sampler_offsets[b] = sampler;
- for (unsigned i = 0; i < array_size; i++) {
- map->sampler_to_descriptor[sampler + i].set = set;
- map->sampler_to_descriptor[sampler + i].offset = set_offset + i;
+ if (binding->data & ANV_DESCRIPTOR_SAMPLER_STATE) {
+ state.set[set].sampler_offsets[b] = map->sampler_count;
+ struct anv_sampler **samplers = binding->immutable_samplers;
+ for (unsigned i = 0; i < binding->array_size; i++) {
+ uint8_t planes = samplers ? samplers[i]->n_planes : 1;
+ for (uint8_t p = 0; p < planes; p++) {
+ map->sampler_to_descriptor[map->sampler_count++] =
+ (struct anv_pipeline_binding) {
+ .set = set,
+ .binding = b,
+ .index = i,
+ .plane = p,
+ };
+ }
}
- sampler += array_size;
}
- if (set_layout->binding[b].stage[shader->stage].image_index >= 0) {
- state.set[set].image_offsets[b] = image;
- image += array_size;
+ if (binding->data & ANV_DESCRIPTOR_IMAGE_PARAM) {
+ state.set[set].image_offsets[b] = map->image_param_count;
+ map->image_param_count += binding->array_size;
}
}
}
- nir_foreach_function(shader, function) {
- if (function->impl) {
- nir_builder_init(&state.builder, function->impl);
- nir_foreach_block(function->impl, apply_pipeline_layout_block, &state);
- nir_metadata_preserve(function->impl, nir_metadata_block_index |
- nir_metadata_dominance);
- }
- }
-
- if (map->image_count > 0) {
- assert(map->image_count <= MAX_IMAGES);
- nir_foreach_variable(var, &shader->uniforms) {
- if (glsl_type_is_image(var->type) ||
- (glsl_type_is_array(var->type) &&
- glsl_type_is_image(glsl_get_array_element(var->type)))) {
- /* Images are represented as uniform push constants and the actual
- * information required for reading/writing to/from the image is
- * storred in the uniform.
- */
- unsigned set = var->data.descriptor_set;
- unsigned binding = var->data.binding;
- unsigned image_index = state.set[set].image_offsets[binding];
-
- var->data.driver_location = shader->num_uniforms +
- image_index * BRW_IMAGE_PARAM_SIZE * 4;
- }
- }
-
+ if (map->image_param_count > 0) {
+ assert(map->image_param_count <= MAX_GEN8_IMAGES);
+ assert(shader->num_uniforms == prog_data->nr_params * 4);
+ state.first_image_uniform = shader->num_uniforms;
+ uint32_t *param = brw_stage_prog_data_add_params(prog_data,
+ map->image_param_count *
+ BRW_IMAGE_PARAM_SIZE);
struct anv_push_constants *null_data = NULL;
- const gl_constant_value **param =
- prog_data->param + (shader->num_uniforms / 4);
const struct brw_image_param *image_param = null_data->images;
- for (uint32_t i = 0; i < map->image_count; i++) {
- setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET,
- (const union gl_constant_value *)&image_param->surface_idx, 1);
+ for (uint32_t i = 0; i < map->image_param_count; i++) {
setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_OFFSET_OFFSET,
- (const union gl_constant_value *)image_param->offset, 2);
+ (uintptr_t)image_param->offset, 2);
setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SIZE_OFFSET,
- (const union gl_constant_value *)image_param->size, 3);
+ (uintptr_t)image_param->size, 3);
setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_STRIDE_OFFSET,
- (const union gl_constant_value *)image_param->stride, 4);
+ (uintptr_t)image_param->stride, 4);
setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_TILING_OFFSET,
- (const union gl_constant_value *)image_param->tiling, 3);
+ (uintptr_t)image_param->tiling, 3);
setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SWIZZLING_OFFSET,
- (const union gl_constant_value *)image_param->swizzling, 2);
+ (uintptr_t)image_param->swizzling, 2);
param += BRW_IMAGE_PARAM_SIZE;
image_param ++;
}
+ assert(param == prog_data->param + prog_data->nr_params);
+
+ shader->num_uniforms += map->image_param_count *
+ BRW_IMAGE_PARAM_SIZE * 4;
+ assert(shader->num_uniforms == prog_data->nr_params * 4);
+ }
+
+ nir_foreach_variable(var, &shader->uniforms) {
+ const struct glsl_type *glsl_type = glsl_without_array(var->type);
+
+ if (!glsl_type_is_image(glsl_type))
+ continue;
+
+ enum glsl_sampler_dim dim = glsl_get_sampler_dim(glsl_type);
+
+ const uint32_t set = var->data.descriptor_set;
+ const uint32_t binding = var->data.binding;
+ const uint32_t array_size =
+ layout->set[set].layout->binding[binding].array_size;
+
+ if (!BITSET_TEST(state.set[set].used, binding))
+ continue;
+
+ struct anv_pipeline_binding *pipe_binding =
+ &map->surface_to_descriptor[state.set[set].surface_offsets[binding]];
+ for (unsigned i = 0; i < array_size; i++) {
+ assert(pipe_binding[i].set == set);
+ assert(pipe_binding[i].binding == binding);
+ assert(pipe_binding[i].index == i);
+
+ if (dim == GLSL_SAMPLER_DIM_SUBPASS ||
+ dim == GLSL_SAMPLER_DIM_SUBPASS_MS)
+ pipe_binding[i].input_attachment_index = var->data.index + i;
+
+ pipe_binding[i].write_only =
+ (var->data.image.access & ACCESS_NON_READABLE) != 0;
+ }
+ }
+
+ nir_foreach_function(function, shader) {
+ if (!function->impl)
+ continue;
- shader->num_uniforms += map->image_count * BRW_IMAGE_PARAM_SIZE * 4;
+ nir_builder_init(&state.builder, function->impl);
+ nir_foreach_block(block, function->impl)
+ apply_pipeline_layout_block(block, &state);
+ nir_metadata_preserve(function->impl, nir_metadata_block_index |
+ nir_metadata_dominance);
}
ralloc_free(mem_ctx);
projects / mesa.git / blobdiff