anv,iris: unbreak on BSDs after 812cf5f522ab,abf8aed68047

[mesa.git] / src / intel / vulkan / anv_nir_apply_pipeline_layout.c

diff --git a/src/intel/vulkan/anv_nir_apply_pipeline_layout.c b/src/intel/vulkan/anv_nir_apply_pipeline_layout.c
index f37b672543b710784b177461bac4264bf78d111c..b5b7cd080411c5b01b834d921830283e49307f87 100644 (file)
--- a/src/intel/vulkan/anv_nir_apply_pipeline_layout.c
+++ b/src/intel/vulkan/anv_nir_apply_pipeline_layout.c
@@ -40,7 +40,7 @@ struct apply_pipeline_layout_state {
    nir_shader *shader;
    nir_builder builder;
 
-   struct anv_pipeline_layout *layout;
+   const struct anv_pipeline_layout *layout;
    bool add_bounds_checks;
    nir_address_format ssbo_addr_format;
 
@@ -534,6 +534,7 @@ build_ssbo_descriptor_load(const VkDescriptorType desc_type,
       nir_intrinsic_instr_create(b->shader, nir_intrinsic_load_ubo);
    desc_load->src[0] = nir_src_for_ssa(desc_buffer_index);
    desc_load->src[1] = nir_src_for_ssa(desc_offset);
+   nir_intrinsic_set_align(desc_load, 8, 0);
    desc_load->num_components = 4;
    nir_ssa_dest_init(&desc_load->instr, &desc_load->dest, 4, 32, NULL);
    nir_builder_instr_insert(b, &desc_load->instr);
@@ -714,6 +715,7 @@ build_descriptor_load(nir_deref_instr *deref, unsigned offset,
       nir_intrinsic_instr_create(b->shader, nir_intrinsic_load_ubo);
    desc_load->src[0] = nir_src_for_ssa(desc_buffer_index);
    desc_load->src[1] = nir_src_for_ssa(desc_offset);
+   nir_intrinsic_set_align(desc_load, 8, offset % 8);
    desc_load->num_components = num_components;
    nir_ssa_dest_init(&desc_load->instr, &desc_load->dest,
                      num_components, bit_size, NULL);
@@ -752,7 +754,7 @@ lower_image_intrinsic(nir_intrinsic_instr *intrin,
       nir_ssa_def_rewrite_uses(&intrin->dest.ssa, nir_src_for_ssa(desc));
    } else if (binding_offset > MAX_BINDING_TABLE_SIZE) {
       const bool write_only =
-         (var->data.image.access & ACCESS_NON_READABLE) != 0;
+         (var->data.access & ACCESS_NON_READABLE) != 0;
       nir_ssa_def *desc =
          build_descriptor_load(deref, 0, 2, 32, state);
       nir_ssa_def *handle = nir_channel(b, desc, write_only ? 1 : 0);
@@ -798,6 +800,7 @@ lower_load_constant(nir_intrinsic_instr *intrin,
    load_ubo->num_components = intrin->num_components;
    load_ubo->src[0] = nir_src_for_ssa(index);
    load_ubo->src[1] = nir_src_for_ssa(offset);
+   nir_intrinsic_set_align(load_ubo, intrin->dest.ssa.bit_size / 8, 0);
    nir_ssa_dest_init(&load_ubo->instr, &load_ubo->dest,
                      intrin->dest.ssa.num_components,
                      intrin->dest.ssa.bit_size, NULL);
@@ -1021,11 +1024,6 @@ lower_tex(nir_tex_instr *tex, struct apply_pipeline_layout_state *state)
 
    lower_tex_deref(tex, nir_tex_src_sampler_deref,
                    &tex->sampler_index, plane, state);
-
-   /* The backend only ever uses this to mark used surfaces.  We don't care
-    * about that little optimization so it just needs to be non-zero.
-    */
-   tex->texture_array_size = 1;
 }
 
 static void
@@ -1107,9 +1105,8 @@ compare_binding_infos(const void *_a, const void *_b)
 void
 anv_nir_apply_pipeline_layout(const struct anv_physical_device *pdevice,
                               bool robust_buffer_access,
-                              struct anv_pipeline_layout *layout,
+                              const struct anv_pipeline_layout *layout,
                               nir_shader *shader,
-                              struct brw_stage_prog_data *prog_data,
                               struct anv_pipeline_bind_map *map)
 {
    void *mem_ctx = ralloc_context(NULL);
@@ -1172,12 +1169,12 @@ anv_nir_apply_pipeline_layout(const struct anv_physical_device *pdevice,
       rzalloc_array(mem_ctx, struct binding_info, used_binding_count);
    used_binding_count = 0;
    for (uint32_t set = 0; set < layout->num_sets; set++) {
-      struct anv_descriptor_set_layout *set_layout = layout->set[set].layout;
+      const struct anv_descriptor_set_layout *set_layout = layout->set[set].layout;
       for (unsigned b = 0; b < set_layout->binding_count; b++) {
          if (state.set[set].use_count[b] == 0)
             continue;
 
-         struct anv_descriptor_set_binding_layout *binding =
+         const struct anv_descriptor_set_binding_layout *binding =
                &layout->set[set].layout->binding[b];
 
          /* Do a fixed-point calculation to generate a score based on the
@@ -1212,7 +1209,7 @@ anv_nir_apply_pipeline_layout(const struct anv_physical_device *pdevice,
 
    for (unsigned i = 0; i < used_binding_count; i++) {
       unsigned set = infos[i].set, b = infos[i].binding;
-      struct anv_descriptor_set_binding_layout *binding =
+      const struct anv_descriptor_set_binding_layout *binding =
             &layout->set[set].layout->binding[b];
 
       const uint32_t array_size = binding->array_size;
@@ -1299,7 +1296,7 @@ anv_nir_apply_pipeline_layout(const struct anv_physical_device *pdevice,
 
       const uint32_t set = var->data.descriptor_set;
       const uint32_t binding = var->data.binding;
-      struct anv_descriptor_set_binding_layout *bind_layout =
+      const struct anv_descriptor_set_binding_layout *bind_layout =
             &layout->set[set].layout->binding[binding];
       const uint32_t array_size = bind_layout->array_size;
 
@@ -1321,7 +1318,7 @@ anv_nir_apply_pipeline_layout(const struct anv_physical_device *pdevice,
 
          /* NOTE: This is a uint8_t so we really do need to != 0 here */
          pipe_binding[i].write_only =
-            (var->data.image.access & ACCESS_NON_READABLE) != 0;
+            (var->data.access & ACCESS_NON_READABLE) != 0;
       }
    }
 
@@ -1329,6 +1326,8 @@ anv_nir_apply_pipeline_layout(const struct anv_physical_device *pdevice,
       if (!function->impl)
          continue;
 
+      nir_builder_init(&state.builder, function->impl);
+
       /* Before we do the normal lowering, we look for any SSBO operations
        * that we can lower to the BTI model and lower them up-front.  The BTI
        * model can perform better than the A64 model for a couple reasons:
@@ -1361,7 +1360,6 @@ anv_nir_apply_pipeline_layout(const struct anv_physical_device *pdevice,
        */
       lower_direct_buffer_access(function->impl, &state);
 
-      nir_builder_init(&state.builder, function->impl);
       nir_foreach_block(block, function->impl)
          apply_pipeline_layout_block(block, &state);
       nir_metadata_preserve(function->impl, nir_metadata_block_index |