#include "util/mesa-sha1.h"
#include "common/gen_l3_config.h"
#include "anv_private.h"
-#include "brw_nir.h"
+#include "compiler/brw_nir.h"
#include "anv_nir.h"
#include "spirv/nir_spirv.h"
ANV_FROM_HANDLE(anv_device, device, _device);
ANV_FROM_HANDLE(anv_shader_module, module, _module);
+ if (!module)
+ return;
+
vk_free2(&device->alloc, pAllocator, module);
}
* we can't do that yet because we don't have the ability to copy nir.
*/
static nir_shader *
-anv_shader_compile_to_nir(struct anv_device *device,
+anv_shader_compile_to_nir(struct anv_pipeline *pipeline,
struct anv_shader_module *module,
const char *entrypoint_name,
gl_shader_stage stage,
const VkSpecializationInfo *spec_info)
{
- if (strcmp(entrypoint_name, "main") != 0) {
- anv_finishme("Multiple shaders per module not really supported");
- }
+ const struct anv_device *device = pipeline->device;
const struct brw_compiler *compiler =
device->instance->physicalDevice.compiler;
assert(data + entry.size <= spec_info->pData + spec_info->dataSize);
spec_entries[i].id = spec_info->pMapEntries[i].constantID;
- spec_entries[i].data = *(const uint32_t *)data;
+ if (spec_info->dataSize == 8)
+ spec_entries[i].data64 = *(const uint64_t *)data;
+ else
+ spec_entries[i].data32 = *(const uint32_t *)data;
}
}
+ const struct nir_spirv_supported_extensions supported_ext = {
+ .float64 = device->instance->physicalDevice.info.gen >= 8,
+ .int64 = device->instance->physicalDevice.info.gen >= 8,
+ .tessellation = true,
+ .draw_parameters = true,
+ .image_write_without_format = true,
+ };
+
nir_function *entry_point =
spirv_to_nir(spirv, module->size / 4,
spec_entries, num_spec_entries,
- stage, entrypoint_name, nir_options);
+ stage, entrypoint_name, &supported_ext, nir_options);
nir_shader *nir = entry_point->shader;
assert(nir->stage == stage);
nir_validate_shader(nir);
free(spec_entries);
- if (stage == MESA_SHADER_FRAGMENT) {
- nir_lower_wpos_center(nir);
- nir_validate_shader(nir);
- }
-
- nir_lower_returns(nir);
- nir_validate_shader(nir);
-
- nir_inline_functions(nir);
- nir_validate_shader(nir);
+ /* We have to lower away local constant initializers right before we
+ * inline functions. That way they get properly initialized at the top
+ * of the function and not at the top of its caller.
+ */
+ NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_local);
+ NIR_PASS_V(nir, nir_lower_returns);
+ NIR_PASS_V(nir, nir_inline_functions);
/* Pick off the single entrypoint that we want */
foreach_list_typed_safe(nir_function, func, node, &nir->functions) {
assert(exec_list_length(&nir->functions) == 1);
entry_point->name = ralloc_strdup(entry_point, "main");
- nir_remove_dead_variables(nir, nir_var_shader_in);
- nir_remove_dead_variables(nir, nir_var_shader_out);
- nir_remove_dead_variables(nir, nir_var_system_value);
- nir_validate_shader(nir);
-
- nir_propagate_invariant(nir);
- nir_validate_shader(nir);
+ NIR_PASS_V(nir, nir_remove_dead_variables,
+ nir_var_shader_in | nir_var_shader_out | nir_var_system_value);
- nir_lower_io_to_temporaries(entry_point->shader, entry_point->impl,
- true, false);
+ if (stage == MESA_SHADER_FRAGMENT)
+ NIR_PASS_V(nir, nir_lower_wpos_center, pipeline->sample_shading_enable);
- nir_lower_system_values(nir);
- nir_validate_shader(nir);
+ /* Now that we've deleted all but the main function, we can go ahead and
+ * lower the rest of the constant initializers.
+ */
+ NIR_PASS_V(nir, nir_lower_constant_initializers, ~0);
+ NIR_PASS_V(nir, nir_propagate_invariant);
+ NIR_PASS_V(nir, nir_lower_io_to_temporaries,
+ entry_point->impl, true, false);
+ NIR_PASS_V(nir, nir_lower_system_values);
/* Vulkan uses the separate-shader linking model */
nir->info->separate_shader = true;
nir = brw_preprocess_nir(compiler, nir);
- nir_shader_gather_info(nir, entry_point->impl);
-
- nir_variable_mode indirect_mask = 0;
- if (compiler->glsl_compiler_options[stage].EmitNoIndirectInput)
- indirect_mask |= nir_var_shader_in;
- if (compiler->glsl_compiler_options[stage].EmitNoIndirectOutput)
- indirect_mask |= nir_var_shader_out;
- if (compiler->glsl_compiler_options[stage].EmitNoIndirectTemp)
- indirect_mask |= nir_var_local;
+ NIR_PASS_V(nir, nir_lower_clip_cull_distance_arrays);
- nir_lower_indirect_derefs(nir, indirect_mask);
+ if (stage == MESA_SHADER_FRAGMENT)
+ NIR_PASS_V(nir, anv_nir_lower_input_attachments);
return nir;
}
ANV_FROM_HANDLE(anv_device, device, _device);
ANV_FROM_HANDLE(anv_pipeline, pipeline, _pipeline);
+ if (!pipeline)
+ return;
+
anv_reloc_list_finish(&pipeline->batch_relocs,
pAllocator ? pAllocator : &device->alloc);
if (pipeline->blend_state.map)
[VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY] = _3DPRIM_LINESTRIP_ADJ,
[VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY] = _3DPRIM_TRILIST_ADJ,
[VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY] = _3DPRIM_TRISTRIP_ADJ,
-/* [VK_PRIMITIVE_TOPOLOGY_PATCH_LIST] = _3DPRIM_PATCHLIST_1 */
};
static void
populate_sampler_prog_key(const struct gen_device_info *devinfo,
struct brw_sampler_prog_key_data *key)
{
+ /* Almost all multisampled textures are compressed. The only time when we
+ * don't compress a multisampled texture is for 16x MSAA with a surface
+ * width greater than 8k which is a bit of an edge case. Since the sampler
+ * just ignores the MCS parameter to ld2ms when MCS is disabled, it's safe
+ * to tell the compiler to always assume compression.
+ */
+ key->compressed_multisample_layout_mask = ~0;
+
+ /* SkyLake added support for 16x MSAA. With this came a new message for
+ * reading from a 16x MSAA surface with compression. The new message was
+ * needed because now the MCS data is 64 bits instead of 32 or lower as is
+ * the case for 8x, 4x, and 2x. The key->msaa_16 bit-field controls which
+ * message we use. Fortunately, the 16x message works for 8x, 4x, and 2x
+ * so we can just use it unconditionally. This may not be quite as
+ * efficient but it saves us from recompiling.
+ */
+ if (devinfo->gen >= 9)
+ key->msaa_16 = ~0;
+
/* XXX: Handle texture swizzle on HSW- */
for (int i = 0; i < MAX_SAMPLERS; i++) {
/* Assume color sampler, no swizzling. (Works for BDW+) */
}
static void
-populate_wm_prog_key(const struct gen_device_info *devinfo,
+populate_wm_prog_key(const struct anv_pipeline *pipeline,
const VkGraphicsPipelineCreateInfo *info,
struct brw_wm_prog_key *key)
{
+ const struct gen_device_info *devinfo = &pipeline->device->info;
ANV_FROM_HANDLE(anv_render_pass, render_pass, info->renderPass);
memset(key, 0, sizeof(*key));
populate_sampler_prog_key(devinfo, &key->tex);
- /* TODO: Fill out key->input_slots_valid */
+ /* TODO: we could set this to 0 based on the information in nir_shader, but
+ * this function is called before spirv_to_nir. */
+ const struct brw_vue_map *vue_map =
+ &anv_pipeline_get_last_vue_prog_data(pipeline)->vue_map;
+ key->input_slots_valid = vue_map->slots_valid;
/* Vulkan doesn't specify a default */
key->high_quality_derivatives = false;
info->pMultisampleState &&
info->pMultisampleState->alphaToCoverageEnable;
- if (info->pMultisampleState && info->pMultisampleState->rasterizationSamples > 1) {
+ if (info->pMultisampleState) {
/* We should probably pull this out of the shader, but it's fairly
* harmless to compute it and then let dead-code take care of it.
*/
- key->persample_interp =
- (info->pMultisampleState->minSampleShading *
- info->pMultisampleState->rasterizationSamples) > 1;
- key->multisample_fbo = true;
+ if (info->pMultisampleState->rasterizationSamples > 1) {
+ key->persample_interp =
+ (info->pMultisampleState->minSampleShading *
+ info->pMultisampleState->rasterizationSamples) > 1;
+ key->multisample_fbo = true;
+ }
+
+ key->frag_coord_adds_sample_pos =
+ info->pMultisampleState->sampleShadingEnable;
}
}
populate_sampler_prog_key(devinfo, &key->tex);
}
+static void
+anv_pipeline_hash_shader(struct anv_pipeline *pipeline,
+ struct anv_shader_module *module,
+ const char *entrypoint,
+ gl_shader_stage stage,
+ const VkSpecializationInfo *spec_info,
+ const void *key, size_t key_size,
+ unsigned char *sha1_out)
+{
+ struct mesa_sha1 ctx;
+
+ _mesa_sha1_init(&ctx);
+ if (pipeline->layout) {
+ _mesa_sha1_update(&ctx, pipeline->layout->sha1,
+ sizeof(pipeline->layout->sha1));
+ }
+ _mesa_sha1_update(&ctx, module->sha1, sizeof(module->sha1));
+ _mesa_sha1_update(&ctx, entrypoint, strlen(entrypoint));
+ _mesa_sha1_update(&ctx, &stage, sizeof(stage));
+ if (spec_info) {
+ _mesa_sha1_update(&ctx, spec_info->pMapEntries,
+ spec_info->mapEntryCount * sizeof(*spec_info->pMapEntries));
+ _mesa_sha1_update(&ctx, spec_info->pData, spec_info->dataSize);
+ }
+ _mesa_sha1_update(&ctx, key, key_size);
+ _mesa_sha1_final(&ctx, sha1_out);
+}
+
static nir_shader *
anv_pipeline_compile(struct anv_pipeline *pipeline,
struct anv_shader_module *module,
struct brw_stage_prog_data *prog_data,
struct anv_pipeline_bind_map *map)
{
- nir_shader *nir = anv_shader_compile_to_nir(pipeline->device,
+ nir_shader *nir = anv_shader_compile_to_nir(pipeline,
module, entrypoint, stage,
spec_info);
if (nir == NULL)
return NULL;
- anv_nir_lower_push_constants(nir);
+ NIR_PASS_V(nir, anv_nir_lower_push_constants);
+
+ nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
/* Figure out the number of parameters */
prog_data->nr_params = 0;
prog_data->nr_params += MAX_PUSH_CONSTANTS_SIZE / sizeof(float);
}
- if (pipeline->layout && pipeline->layout->stage[stage].has_dynamic_offsets)
- prog_data->nr_params += MAX_DYNAMIC_BUFFERS * 2;
-
if (nir->info->num_images > 0) {
prog_data->nr_params += nir->info->num_images * BRW_IMAGE_PARAM_SIZE;
pipeline->needs_data_cache = true;
}
}
- /* Set up dynamic offsets */
- anv_nir_apply_dynamic_offsets(pipeline, nir, prog_data);
-
/* Apply the actual pipeline layout to UBOs, SSBOs, and textures */
if (pipeline->layout)
anv_nir_apply_pipeline_layout(pipeline, nir, prog_data, map);
populate_vs_prog_key(&pipeline->device->info, &key);
if (cache) {
- anv_hash_shader(sha1, &key, sizeof(key), module, entrypoint,
- pipeline->layout, spec_info);
+ anv_pipeline_hash_shader(pipeline, module, entrypoint,
+ MESA_SHADER_VERTEX, spec_info,
+ &key, sizeof(key), sha1);
bin = anv_pipeline_cache_search(cache, sha1, 20);
}
ralloc_steal(mem_ctx, nir);
prog_data.inputs_read = nir->info->inputs_read;
+ prog_data.double_inputs_read = nir->info->double_inputs_read;
brw_compute_vue_map(&pipeline->device->info,
&prog_data.base.vue_map,
ralloc_free(mem_ctx);
}
- const struct brw_vs_prog_data *vs_prog_data =
- (const struct brw_vs_prog_data *)bin->prog_data;
+ anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_VERTEX, bin);
- if (vs_prog_data->base.dispatch_mode == DISPATCH_MODE_SIMD8) {
- pipeline->vs_simd8 = bin->kernel.offset;
- pipeline->vs_vec4 = NO_KERNEL;
- } else {
- pipeline->vs_simd8 = NO_KERNEL;
- pipeline->vs_vec4 = bin->kernel.offset;
+ return VK_SUCCESS;
+}
+
+static void
+merge_tess_info(struct shader_info *tes_info,
+ const struct shader_info *tcs_info)
+{
+ /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
+ *
+ * "PointMode. Controls generation of points rather than triangles
+ * or lines. This functionality defaults to disabled, and is
+ * enabled if either shader stage includes the execution mode.
+ *
+ * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
+ * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
+ * and OutputVertices, it says:
+ *
+ * "One mode must be set in at least one of the tessellation
+ * shader stages."
+ *
+ * So, the fields can be set in either the TCS or TES, but they must
+ * agree if set in both. Our backend looks at TES, so bitwise-or in
+ * the values from the TCS.
+ */
+ assert(tcs_info->tess.tcs_vertices_out == 0 ||
+ tes_info->tess.tcs_vertices_out == 0 ||
+ tcs_info->tess.tcs_vertices_out == tes_info->tess.tcs_vertices_out);
+ tes_info->tess.tcs_vertices_out |= tcs_info->tess.tcs_vertices_out;
+
+ assert(tcs_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
+ tes_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
+ tcs_info->tess.spacing == tes_info->tess.spacing);
+ tes_info->tess.spacing |= tcs_info->tess.spacing;
+
+ tes_info->tess.ccw |= tcs_info->tess.ccw;
+ tes_info->tess.point_mode |= tcs_info->tess.point_mode;
+}
+
+static VkResult
+anv_pipeline_compile_tcs_tes(struct anv_pipeline *pipeline,
+ struct anv_pipeline_cache *cache,
+ const VkGraphicsPipelineCreateInfo *info,
+ struct anv_shader_module *tcs_module,
+ const char *tcs_entrypoint,
+ const VkSpecializationInfo *tcs_spec_info,
+ struct anv_shader_module *tes_module,
+ const char *tes_entrypoint,
+ const VkSpecializationInfo *tes_spec_info)
+{
+ const struct gen_device_info *devinfo = &pipeline->device->info;
+ const struct brw_compiler *compiler =
+ pipeline->device->instance->physicalDevice.compiler;
+ struct anv_pipeline_bind_map tcs_map;
+ struct anv_pipeline_bind_map tes_map;
+ struct brw_tcs_prog_key tcs_key = { 0, };
+ struct brw_tes_prog_key tes_key = { 0, };
+ struct anv_shader_bin *tcs_bin = NULL;
+ struct anv_shader_bin *tes_bin = NULL;
+ unsigned char tcs_sha1[40];
+ unsigned char tes_sha1[40];
+
+ populate_sampler_prog_key(&pipeline->device->info, &tcs_key.tex);
+ populate_sampler_prog_key(&pipeline->device->info, &tes_key.tex);
+ tcs_key.input_vertices = info->pTessellationState->patchControlPoints;
+
+ if (cache) {
+ anv_pipeline_hash_shader(pipeline, tcs_module, tcs_entrypoint,
+ MESA_SHADER_TESS_CTRL, tcs_spec_info,
+ &tcs_key, sizeof(tcs_key), tcs_sha1);
+ anv_pipeline_hash_shader(pipeline, tes_module, tes_entrypoint,
+ MESA_SHADER_TESS_EVAL, tes_spec_info,
+ &tes_key, sizeof(tes_key), tes_sha1);
+ memcpy(&tcs_sha1[20], tes_sha1, 20);
+ memcpy(&tes_sha1[20], tcs_sha1, 20);
+ tcs_bin = anv_pipeline_cache_search(cache, tcs_sha1, sizeof(tcs_sha1));
+ tes_bin = anv_pipeline_cache_search(cache, tes_sha1, sizeof(tes_sha1));
}
- anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_VERTEX, bin);
+ if (tcs_bin == NULL || tes_bin == NULL) {
+ struct brw_tcs_prog_data tcs_prog_data = { 0, };
+ struct brw_tes_prog_data tes_prog_data = { 0, };
+ struct anv_pipeline_binding tcs_surface_to_descriptor[256];
+ struct anv_pipeline_binding tcs_sampler_to_descriptor[256];
+ struct anv_pipeline_binding tes_surface_to_descriptor[256];
+ struct anv_pipeline_binding tes_sampler_to_descriptor[256];
+
+ tcs_map = (struct anv_pipeline_bind_map) {
+ .surface_to_descriptor = tcs_surface_to_descriptor,
+ .sampler_to_descriptor = tcs_sampler_to_descriptor
+ };
+ tes_map = (struct anv_pipeline_bind_map) {
+ .surface_to_descriptor = tes_surface_to_descriptor,
+ .sampler_to_descriptor = tes_sampler_to_descriptor
+ };
+
+ nir_shader *tcs_nir =
+ anv_pipeline_compile(pipeline, tcs_module, tcs_entrypoint,
+ MESA_SHADER_TESS_CTRL, tcs_spec_info,
+ &tcs_prog_data.base.base, &tcs_map);
+ nir_shader *tes_nir =
+ anv_pipeline_compile(pipeline, tes_module, tes_entrypoint,
+ MESA_SHADER_TESS_EVAL, tes_spec_info,
+ &tes_prog_data.base.base, &tes_map);
+ if (tcs_nir == NULL || tes_nir == NULL)
+ return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
+
+ nir_lower_tes_patch_vertices(tes_nir,
+ tcs_nir->info->tess.tcs_vertices_out);
+
+ /* Copy TCS info into the TES info */
+ merge_tess_info(tes_nir->info, tcs_nir->info);
+
+ anv_fill_binding_table(&tcs_prog_data.base.base, 0);
+ anv_fill_binding_table(&tes_prog_data.base.base, 0);
+
+ void *mem_ctx = ralloc_context(NULL);
+
+ ralloc_steal(mem_ctx, tcs_nir);
+ ralloc_steal(mem_ctx, tes_nir);
+
+ /* Whacking the key after cache lookup is a bit sketchy, but all of
+ * this comes from the SPIR-V, which is part of the hash used for the
+ * pipeline cache. So it should be safe.
+ */
+ tcs_key.tes_primitive_mode = tes_nir->info->tess.primitive_mode;
+ tcs_key.outputs_written = tcs_nir->info->outputs_written;
+ tcs_key.patch_outputs_written = tcs_nir->info->patch_outputs_written;
+ tcs_key.quads_workaround =
+ devinfo->gen < 9 &&
+ tes_nir->info->tess.primitive_mode == 7 /* GL_QUADS */ &&
+ tes_nir->info->tess.spacing == TESS_SPACING_EQUAL;
+
+ tes_key.inputs_read = tcs_key.outputs_written;
+ tes_key.patch_inputs_read = tcs_key.patch_outputs_written;
+
+ unsigned code_size;
+ const int shader_time_index = -1;
+ const unsigned *shader_code;
+
+ shader_code =
+ brw_compile_tcs(compiler, NULL, mem_ctx, &tcs_key, &tcs_prog_data,
+ tcs_nir, shader_time_index, &code_size, NULL);
+ if (shader_code == NULL) {
+ ralloc_free(mem_ctx);
+ return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
+ }
+
+ tcs_bin = anv_pipeline_upload_kernel(pipeline, cache,
+ tcs_sha1, sizeof(tcs_sha1),
+ shader_code, code_size,
+ &tcs_prog_data.base.base,
+ sizeof(tcs_prog_data),
+ &tcs_map);
+ if (!tcs_bin) {
+ ralloc_free(mem_ctx);
+ return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
+ }
+
+ shader_code =
+ brw_compile_tes(compiler, NULL, mem_ctx, &tes_key,
+ &tcs_prog_data.base.vue_map, &tes_prog_data, tes_nir,
+ NULL, shader_time_index, &code_size, NULL);
+ if (shader_code == NULL) {
+ ralloc_free(mem_ctx);
+ return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
+ }
+
+ tes_bin = anv_pipeline_upload_kernel(pipeline, cache,
+ tes_sha1, sizeof(tes_sha1),
+ shader_code, code_size,
+ &tes_prog_data.base.base,
+ sizeof(tes_prog_data),
+ &tes_map);
+ if (!tes_bin) {
+ ralloc_free(mem_ctx);
+ return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
+ }
+
+ ralloc_free(mem_ctx);
+ }
+
+ anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_TESS_CTRL, tcs_bin);
+ anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_TESS_EVAL, tes_bin);
return VK_SUCCESS;
}
populate_gs_prog_key(&pipeline->device->info, &key);
if (cache) {
- anv_hash_shader(sha1, &key, sizeof(key), module, entrypoint,
- pipeline->layout, spec_info);
+ anv_pipeline_hash_shader(pipeline, module, entrypoint,
+ MESA_SHADER_GEOMETRY, spec_info,
+ &key, sizeof(key), sha1);
bin = anv_pipeline_cache_search(cache, sha1, 20);
}
ralloc_free(mem_ctx);
}
- pipeline->gs_kernel = bin->kernel.offset;
-
anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_GEOMETRY, bin);
return VK_SUCCESS;
struct anv_shader_bin *bin = NULL;
unsigned char sha1[20];
- populate_wm_prog_key(&pipeline->device->info, info, &key);
+ populate_wm_prog_key(pipeline, info, &key);
if (cache) {
- anv_hash_shader(sha1, &key, sizeof(key), module, entrypoint,
- pipeline->layout, spec_info);
+ anv_pipeline_hash_shader(pipeline, module, entrypoint,
+ MESA_SHADER_FRAGMENT, spec_info,
+ &key, sizeof(key), sha1);
bin = anv_pipeline_cache_search(cache, sha1, 20);
}
ralloc_free(mem_ctx);
}
- pipeline->ps_ksp0 = bin->kernel.offset;
-
anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_FRAGMENT, bin);
return VK_SUCCESS;
populate_cs_prog_key(&pipeline->device->info, &key);
if (cache) {
- anv_hash_shader(sha1, &key, sizeof(key), module, entrypoint,
- pipeline->layout, spec_info);
+ anv_pipeline_hash_shader(pipeline, module, entrypoint,
+ MESA_SHADER_COMPUTE, spec_info,
+ &key, sizeof(key), sha1);
bin = anv_pipeline_cache_search(cache, sha1, 20);
}
ralloc_free(mem_ctx);
}
- pipeline->cs_simd = bin->kernel.offset;
-
anv_pipeline_add_compiled_stage(pipeline, MESA_SHADER_COMPUTE, bin);
return VK_SUCCESS;
*/
bool uses_color_att = false;
for (unsigned i = 0; i < subpass->color_count; ++i) {
- if (subpass->color_attachments[i] != VK_ATTACHMENT_UNUSED) {
+ if (subpass->color_attachments[i].attachment != VK_ATTACHMENT_UNUSED) {
uses_color_att = true;
break;
}
* against does not use a depth/stencil attachment.
*/
if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
- subpass->depth_stencil_attachment != VK_ATTACHMENT_UNUSED) {
+ subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) {
assert(pCreateInfo->pDepthStencilState);
if (states & (1 << VK_DYNAMIC_STATE_DEPTH_BOUNDS)) {
static void
anv_pipeline_validate_create_info(const VkGraphicsPipelineCreateInfo *info)
{
+#ifdef DEBUG
struct anv_render_pass *renderpass = NULL;
struct anv_subpass *subpass = NULL;
assert(info->pViewportState);
assert(info->pMultisampleState);
- if (subpass && subpass->depth_stencil_attachment != VK_ATTACHMENT_UNUSED)
+ if (subpass && subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED)
assert(info->pDepthStencilState);
if (subpass && subpass->color_count > 0)
break;
}
}
+#endif
}
/**
{
VkResult result;
- anv_validate {
- anv_pipeline_validate_create_info(pCreateInfo);
- }
+ anv_pipeline_validate_create_info(pCreateInfo);
if (alloc == NULL)
alloc = &device->alloc;
pipeline->batch.next = pipeline->batch.start = pipeline->batch_data;
pipeline->batch.end = pipeline->batch.start + sizeof(pipeline->batch_data);
pipeline->batch.relocs = &pipeline->batch_relocs;
+ pipeline->batch.status = VK_SUCCESS;
copy_non_dynamic_state(pipeline, pCreateInfo);
pipeline->depth_clamp_enable = pCreateInfo->pRasterizationState &&
pCreateInfo->pRasterizationState->depthClampEnable;
+ pipeline->sample_shading_enable = pCreateInfo->pMultisampleState &&
+ pCreateInfo->pMultisampleState->sampleShadingEnable;
+
pipeline->needs_data_cache = false;
/* When we free the pipeline, we detect stages based on the NULL status
*/
memset(pipeline->shaders, 0, sizeof(pipeline->shaders));
- pipeline->vs_simd8 = NO_KERNEL;
- pipeline->vs_vec4 = NO_KERNEL;
- pipeline->gs_kernel = NO_KERNEL;
- pipeline->ps_ksp0 = NO_KERNEL;
-
pipeline->active_stages = 0;
const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
goto compile_fail;
}
- if (modules[MESA_SHADER_TESS_CTRL] || modules[MESA_SHADER_TESS_EVAL])
- anv_finishme("no tessellation support");
+ if (modules[MESA_SHADER_TESS_EVAL]) {
+ anv_pipeline_compile_tcs_tes(pipeline, cache, pCreateInfo,
+ modules[MESA_SHADER_TESS_CTRL],
+ pStages[MESA_SHADER_TESS_CTRL]->pName,
+ pStages[MESA_SHADER_TESS_CTRL]->pSpecializationInfo,
+ modules[MESA_SHADER_TESS_EVAL],
+ pStages[MESA_SHADER_TESS_EVAL]->pName,
+ pStages[MESA_SHADER_TESS_EVAL]->pSpecializationInfo);
+ }
if (modules[MESA_SHADER_GEOMETRY]) {
result = anv_pipeline_compile_gs(pipeline, cache, pCreateInfo,
const VkPipelineInputAssemblyStateCreateInfo *ia_info =
pCreateInfo->pInputAssemblyState;
+ const VkPipelineTessellationStateCreateInfo *tess_info =
+ pCreateInfo->pTessellationState;
pipeline->primitive_restart = ia_info->primitiveRestartEnable;
- pipeline->topology = vk_to_gen_primitive_type[ia_info->topology];
+
+ if (anv_pipeline_has_stage(pipeline, MESA_SHADER_TESS_EVAL))
+ pipeline->topology = _3DPRIM_PATCHLIST(tess_info->patchControlPoints);
+ else
+ pipeline->topology = vk_to_gen_primitive_type[ia_info->topology];
return VK_SUCCESS;
projects / mesa.git / blobdiff