anv: Clarify behavior of anv_image_aspect_to_plane()

[mesa.git] / src / intel / vulkan / anv_pipeline.c

diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c
index aee3b22193795ae129c9db8170b33d5d6ab5158d..e6958c40ce674e3c9f68c53b576eb125c1b9f961 100644 (file)
--- a/src/intel/vulkan/anv_pipeline.c
+++ b/src/intel/vulkan/anv_pipeline.c
@@ -107,6 +107,8 @@ static void anv_spirv_nir_debug(void *private_data,
                                 const char *message)
 {
    struct anv_spirv_debug_data *debug_data = private_data;
+   struct anv_instance *instance = debug_data->device->physical->instance;
+
    static const VkDebugReportFlagsEXT vk_flags[] = {
       [NIR_SPIRV_DEBUG_LEVEL_INFO] = VK_DEBUG_REPORT_INFORMATION_BIT_EXT,
       [NIR_SPIRV_DEBUG_LEVEL_WARNING] = VK_DEBUG_REPORT_WARNING_BIT_EXT,
@@ -116,7 +118,7 @@ static void anv_spirv_nir_debug(void *private_data,
 
    snprintf(buffer, sizeof(buffer), "SPIR-V offset %lu: %s", (unsigned long) spirv_offset, message);
 
-   vk_debug_report(&debug_data->device->instance->debug_report_callbacks,
+   vk_debug_report(&instance->debug_report_callbacks,
                    vk_flags[level],
                    VK_DEBUG_REPORT_OBJECT_TYPE_SHADER_MODULE_EXT,
                    (uint64_t) (uintptr_t) debug_data->module,
@@ -134,8 +136,7 @@ anv_shader_compile_to_nir(struct anv_device *device,
                           gl_shader_stage stage,
                           const VkSpecializationInfo *spec_info)
 {
-   const struct anv_physical_device *pdevice =
-      &device->instance->physicalDevice;
+   const struct anv_physical_device *pdevice = device->physical;
    const struct brw_compiler *compiler = pdevice->compiler;
    const nir_shader_compiler_options *nir_options =
       compiler->glsl_compiler_options[stage].NirOptions;
@@ -187,6 +188,7 @@ anv_shader_compile_to_nir(struct anv_device *device,
          .int16 = pdevice->info.gen >= 8,
          .int64 = pdevice->info.gen >= 8,
          .int64_atomics = pdevice->info.gen >= 9 && pdevice->use_softpin,
+         .integer_functions2 = pdevice->info.gen >= 8,
          .min_lod = true,
          .multiview = true,
          .physical_storage_buffer_address = pdevice->has_a64_buffer_access,
@@ -248,7 +250,7 @@ anv_shader_compile_to_nir(struct anv_device *device,
     * inline functions.  That way they get properly initialized at the top
     * of the function and not at the top of its caller.
     */
-   NIR_PASS_V(nir, nir_lower_constant_initializers, nir_var_function_temp);
+   NIR_PASS_V(nir, nir_lower_variable_initializers, nir_var_function_temp);
    NIR_PASS_V(nir, nir_lower_returns);
    NIR_PASS_V(nir, nir_inline_functions);
    NIR_PASS_V(nir, nir_opt_deref);
@@ -265,7 +267,7 @@ anv_shader_compile_to_nir(struct anv_device *device,
     * nir_remove_dead_variables and split_per_member_structs below see the
     * corresponding stores.
     */
-   NIR_PASS_V(nir, nir_lower_constant_initializers, ~0);
+   NIR_PASS_V(nir, nir_lower_variable_initializers, ~0);
 
    /* Split member structs.  We do this before lower_io_to_temporaries so that
     * it doesn't lower system values to temporaries by accident.
@@ -624,7 +626,7 @@ anv_pipeline_stage_get_nir(struct anv_pipeline *pipeline,
                            struct anv_pipeline_stage *stage)
 {
    const struct brw_compiler *compiler =
-      pipeline->device->instance->physicalDevice.compiler;
+      pipeline->device->physical->compiler;
    const nir_shader_compiler_options *nir_options =
       compiler->glsl_compiler_options[stage->stage].NirOptions;
    nir_shader *nir;
@@ -658,8 +660,7 @@ anv_pipeline_lower_nir(struct anv_pipeline *pipeline,
                        struct anv_pipeline_stage *stage,
                        struct anv_pipeline_layout *layout)
 {
-   const struct anv_physical_device *pdevice =
-      &pipeline->device->instance->physicalDevice;
+   const struct anv_physical_device *pdevice = pipeline->device->physical;
    const struct brw_compiler *compiler = pdevice->compiler;
 
    struct brw_stage_prog_data *prog_data = &stage->prog_data.base;
@@ -688,8 +689,7 @@ anv_pipeline_lower_nir(struct anv_pipeline *pipeline,
    /* Apply the actual pipeline layout to UBOs, SSBOs, and textures */
    anv_nir_apply_pipeline_layout(pdevice,
                                  pipeline->device->robust_buffer_access,
-                                 layout, nir, prog_data,
-                                 &stage->bind_map);
+                                 layout, nir, &stage->bind_map);
 
    NIR_PASS_V(nir, nir_lower_explicit_io, nir_var_mem_ubo,
               nir_address_format_32bit_index_offset);
@@ -1115,8 +1115,7 @@ anv_pipeline_compile_graphics(struct anv_pipeline *pipeline,
    };
    int64_t pipeline_start = os_time_get_nano();
 
-   const struct brw_compiler *compiler =
-      pipeline->device->instance->physicalDevice.compiler;
+   const struct brw_compiler *compiler = pipeline->device->physical->compiler;
    struct anv_pipeline_stage stages[MESA_SHADER_STAGES] = {};
 
    pipeline->active_stages = 0;
@@ -1156,12 +1155,15 @@ anv_pipeline_compile_graphics(struct anv_pipeline *pipeline,
       case MESA_SHADER_GEOMETRY:
          populate_gs_prog_key(devinfo, sinfo->flags, &stages[stage].key.gs);
          break;
-      case MESA_SHADER_FRAGMENT:
+      case MESA_SHADER_FRAGMENT: {
+         const bool raster_enabled =
+            !info->pRasterizationState->rasterizerDiscardEnable;
          populate_wm_prog_key(devinfo, sinfo->flags,
                               pipeline->subpass,
-                              info->pMultisampleState,
+                              raster_enabled ? info->pMultisampleState : NULL,
                               &stages[stage].key.wm);
          break;
+      }
       default:
          unreachable("Invalid graphics shader stage");
       }
@@ -1239,7 +1241,7 @@ anv_pipeline_compile_graphics(struct anv_pipeline *pipeline,
           */
          assert(found < __builtin_popcount(pipeline->active_stages));
 
-         vk_debug_report(&pipeline->device->instance->debug_report_callbacks,
+         vk_debug_report(&pipeline->device->physical->instance->debug_report_callbacks,
                          VK_DEBUG_REPORT_WARNING_BIT_EXT |
                          VK_DEBUG_REPORT_PERFORMANCE_WARNING_BIT_EXT,
                          VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_CACHE_EXT,
@@ -1464,8 +1466,7 @@ anv_pipeline_compile_cs(struct anv_pipeline *pipeline,
    };
    int64_t pipeline_start = os_time_get_nano();
 
-   const struct brw_compiler *compiler =
-      pipeline->device->instance->physicalDevice.compiler;
+   const struct brw_compiler *compiler = pipeline->device->physical->compiler;
 
    struct anv_pipeline_stage stage = {
       .stage = MESA_SHADER_COMPUTE,
@@ -1862,9 +1863,10 @@ anv_pipeline_init(struct anv_pipeline *pipeline,
    pipeline->mem_ctx = ralloc_context(NULL);
    pipeline->flags = pCreateInfo->flags;
 
+   assert(pCreateInfo->pRasterizationState);
+
    copy_non_dynamic_state(pipeline, pCreateInfo);
-   pipeline->depth_clamp_enable = pCreateInfo->pRasterizationState &&
-                                  pCreateInfo->pRasterizationState->depthClampEnable;
+   pipeline->depth_clamp_enable = pCreateInfo->pRasterizationState->depthClampEnable;
 
    /* Previously we enabled depth clipping when !depthClampEnable.
     * DepthClipStateCreateInfo now makes depth clipping explicit so if the
@@ -1876,8 +1878,10 @@ anv_pipeline_init(struct anv_pipeline *pipeline,
                            PIPELINE_RASTERIZATION_DEPTH_CLIP_STATE_CREATE_INFO_EXT);
    pipeline->depth_clip_enable = clip_info ? clip_info->depthClipEnable : !pipeline->depth_clamp_enable;
 
-   pipeline->sample_shading_enable = pCreateInfo->pMultisampleState &&
-                                     pCreateInfo->pMultisampleState->sampleShadingEnable;
+   pipeline->sample_shading_enable =
+      !pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
+      pCreateInfo->pMultisampleState &&
+      pCreateInfo->pMultisampleState->sampleShadingEnable;
 
    pipeline->needs_data_cache = false;