iris/bufmgr: Initialize aux map context for gen12
[mesa.git] / src / intel / vulkan / anv_pipeline_cache.c
index ad1bcf0940fcdeb43d5b4bb57faf03b1a80e66c0..e1d48b879b07effede1be87a0355a76b0e36a120 100644 (file)
@@ -21,7 +21,7 @@
  * IN THE SOFTWARE.
  */
 
-#include "compiler/blob.h"
+#include "util/blob.h"
 #include "util/hash_table.h"
 #include "util/debug.h"
 #include "util/disk_cache.h"
@@ -37,6 +37,7 @@ anv_shader_bin_create(struct anv_device *device,
                       const void *constant_data, uint32_t constant_data_size,
                       const struct brw_stage_prog_data *prog_data_in,
                       uint32_t prog_data_size, const void *prog_data_param_in,
+                      const struct brw_compile_stats *stats, uint32_t num_stats,
                       const nir_xfb_info *xfb_info_in,
                       const struct anv_pipeline_bind_map *bind_map)
 {
@@ -93,6 +94,10 @@ anv_shader_bin_create(struct anv_device *device,
    shader->prog_data = prog_data;
    shader->prog_data_size = prog_data_size;
 
+   assert(num_stats <= ARRAY_SIZE(shader->stats));
+   typed_memcpy(shader->stats, stats, num_stats);
+   shader->num_stats = num_stats;
+
    if (xfb_info_in) {
       *xfb_info = *xfb_info_in;
       typed_memcpy(xfb_info->outputs, xfb_info_in->outputs,
@@ -143,6 +148,10 @@ anv_shader_bin_write_to_blob(const struct anv_shader_bin *shader,
                     shader->prog_data->nr_params *
                     sizeof(*shader->prog_data->param));
 
+   blob_write_uint32(blob, shader->num_stats);
+   blob_write_bytes(blob, shader->stats,
+                    shader->num_stats * sizeof(shader->stats[0]));
+
    if (shader->xfb_info) {
       uint32_t xfb_info_size =
          nir_xfb_info_size(shader->xfb_info->output_count);
@@ -154,7 +163,6 @@ anv_shader_bin_write_to_blob(const struct anv_shader_bin *shader,
 
    blob_write_uint32(blob, shader->bind_map.surface_count);
    blob_write_uint32(blob, shader->bind_map.sampler_count);
-   blob_write_uint32(blob, shader->bind_map.image_count);
    blob_write_bytes(blob, shader->bind_map.surface_to_descriptor,
                     shader->bind_map.surface_count *
                     sizeof(*shader->bind_map.surface_to_descriptor));
@@ -186,6 +194,10 @@ anv_shader_bin_create_from_blob(struct anv_device *device,
    const void *prog_data_param =
       blob_read_bytes(blob, prog_data->nr_params * sizeof(*prog_data->param));
 
+   uint32_t num_stats = blob_read_uint32(blob);
+   const struct brw_compile_stats *stats =
+      blob_read_bytes(blob, num_stats * sizeof(stats[0]));
+
    const nir_xfb_info *xfb_info = NULL;
    uint32_t xfb_size = blob_read_uint32(blob);
    if (xfb_size)
@@ -194,7 +206,6 @@ anv_shader_bin_create_from_blob(struct anv_device *device,
    struct anv_pipeline_bind_map bind_map;
    bind_map.surface_count = blob_read_uint32(blob);
    bind_map.sampler_count = blob_read_uint32(blob);
-   bind_map.image_count = blob_read_uint32(blob);
    bind_map.surface_to_descriptor = (void *)
       blob_read_bytes(blob, bind_map.surface_count *
                             sizeof(*bind_map.surface_to_descriptor));
@@ -210,7 +221,7 @@ anv_shader_bin_create_from_blob(struct anv_device *device,
                                 kernel_data, kernel_size,
                                 constant_data, constant_data_size,
                                 prog_data, prog_data_size, prog_data_param,
-                                xfb_info, &bind_map);
+                                stats, num_stats, xfb_info, &bind_map);
 }
 
 /* Remaining work:
@@ -361,6 +372,8 @@ anv_pipeline_cache_add_shader_locked(struct anv_pipeline_cache *cache,
                                      const struct brw_stage_prog_data *prog_data,
                                      uint32_t prog_data_size,
                                      const void *prog_data_param,
+                                     const struct brw_compile_stats *stats,
+                                     uint32_t num_stats,
                                      const nir_xfb_info *xfb_info,
                                      const struct anv_pipeline_bind_map *bind_map)
 {
@@ -374,7 +387,7 @@ anv_pipeline_cache_add_shader_locked(struct anv_pipeline_cache *cache,
                             kernel_data, kernel_size,
                             constant_data, constant_data_size,
                             prog_data, prog_data_size, prog_data_param,
-                            xfb_info, bind_map);
+                            stats, num_stats, xfb_info, bind_map);
    if (!bin)
       return NULL;
 
@@ -391,6 +404,8 @@ anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache *cache,
                                  uint32_t constant_data_size,
                                  const struct brw_stage_prog_data *prog_data,
                                  uint32_t prog_data_size,
+                                 const struct brw_compile_stats *stats,
+                                 uint32_t num_stats,
                                  const nir_xfb_info *xfb_info,
                                  const struct anv_pipeline_bind_map *bind_map)
 {
@@ -403,6 +418,7 @@ anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache *cache,
                                               constant_data, constant_data_size,
                                               prog_data, prog_data_size,
                                               prog_data->param,
+                                              stats, num_stats,
                                               xfb_info, bind_map);
 
       pthread_mutex_unlock(&cache->mutex);
@@ -419,6 +435,7 @@ anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache *cache,
                                    constant_data, constant_data_size,
                                    prog_data, prog_data_size,
                                    prog_data->param,
+                                   stats, num_stats,
                                    xfb_info, bind_map);
    }
 }
@@ -611,14 +628,19 @@ VkResult anv_MergePipelineCaches(
 struct anv_shader_bin *
 anv_device_search_for_kernel(struct anv_device *device,
                              struct anv_pipeline_cache *cache,
-                             const void *key_data, uint32_t key_size)
+                             const void *key_data, uint32_t key_size,
+                             bool *user_cache_hit)
 {
    struct anv_shader_bin *bin;
 
+   *user_cache_hit = false;
+
    if (cache) {
       bin = anv_pipeline_cache_search(cache, key_data, key_size);
-      if (bin)
+      if (bin) {
+         *user_cache_hit = cache != &device->default_pipeline_cache;
          return bin;
+      }
    }
 
 #ifdef ENABLE_SHADER_CACHE
@@ -656,6 +678,8 @@ anv_device_upload_kernel(struct anv_device *device,
                          uint32_t constant_data_size,
                          const struct brw_stage_prog_data *prog_data,
                          uint32_t prog_data_size,
+                         const struct brw_compile_stats *stats,
+                         uint32_t num_stats,
                          const nir_xfb_info *xfb_info,
                          const struct anv_pipeline_bind_map *bind_map)
 {
@@ -665,6 +689,7 @@ anv_device_upload_kernel(struct anv_device *device,
                                              kernel_data, kernel_size,
                                              constant_data, constant_data_size,
                                              prog_data, prog_data_size,
+                                             stats, num_stats,
                                              xfb_info, bind_map);
    } else {
       bin = anv_shader_bin_create(device, key_data, key_size,
@@ -672,6 +697,7 @@ anv_device_upload_kernel(struct anv_device *device,
                                   constant_data, constant_data_size,
                                   prog_data, prog_data_size,
                                   prog_data->param,
+                                  stats, num_stats,
                                   xfb_info, bind_map);
    }
 
@@ -753,7 +779,7 @@ anv_device_upload_nir(struct anv_device *device,
       struct blob blob;
       blob_init(&blob);
 
-      nir_serialize(&blob, nir);
+      nir_serialize(&blob, nir, false);
       if (blob.out_of_memory) {
          blob_finish(&blob);
          return;
@@ -766,6 +792,7 @@ anv_device_upload_nir(struct anv_device *device,
        */
       entry = _mesa_hash_table_search(cache->nir_cache, sha1_key);
       if (entry) {
+         blob_finish(&blob);
          pthread_mutex_unlock(&cache->mutex);
          return;
       }
@@ -776,6 +803,8 @@ anv_device_upload_nir(struct anv_device *device,
       snir->size = blob.size;
       memcpy(snir->data, blob.data, blob.size);
 
+      blob_finish(&blob);
+
       _mesa_hash_table_insert(cache->nir_cache, snir->sha1_key, snir);
 
       pthread_mutex_unlock(&cache->mutex);