}
}
+static inline union isl_color_value
+vk_to_isl_color(VkClearColorValue color)
+{
+ return (union isl_color_value) {
+ .u32 = {
+ color.uint32[0],
+ color.uint32[1],
+ color.uint32[2],
+ color.uint32[3],
+ },
+ };
+}
+
#define for_each_bit(b, dword) \
for (uint32_t __dword = (dword); \
(b) = __builtin_ffs(__dword) - 1, __dword; \
__dword &= ~(1 << (b)))
#define typed_memcpy(dest, src, count) ({ \
- static_assert(sizeof(*src) == sizeof(*dest), ""); \
+ STATIC_ASSERT(sizeof(*src) == sizeof(*dest)); \
memcpy((dest), (src), (count) * sizeof(*(src))); \
})
/**
* Print a FINISHME message, including its source location.
*/
-#define anv_finishme(format, ...) ({ \
- static bool reported = false; \
- if (!reported) { \
- __anv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
- reported = true; \
- } \
-})
+#define anv_finishme(format, ...) \
+ do { \
+ static bool reported = false; \
+ if (!reported) { \
+ __anv_finishme(__FILE__, __LINE__, format, ##__VA_ARGS__); \
+ reported = true; \
+ } \
+ } while (0)
/* A non-fatal assert. Useful for debugging. */
#ifdef DEBUG
anv_clflush_range(state.map, state.alloc_size);
}
-void anv_block_pool_init(struct anv_block_pool *pool,
- struct anv_device *device, uint32_t block_size);
+VkResult anv_block_pool_init(struct anv_block_pool *pool,
+ struct anv_device *device, uint32_t block_size);
void anv_block_pool_finish(struct anv_block_pool *pool);
int32_t anv_block_pool_alloc(struct anv_block_pool *pool);
int32_t anv_block_pool_alloc_back(struct anv_block_pool *pool);
uint32_t eu_total;
uint32_t subslice_total;
+ uint8_t uuid[VK_UUID_SIZE];
+
struct wsi_device wsi_device;
};
uint32_t default_mocs;
pthread_mutex_t mutex;
+ pthread_cond_t queue_submit;
};
-void anv_device_get_cache_uuid(void *uuid);
-
void anv_device_init_blorp(struct anv_device *device);
void anv_device_finish_blorp(struct anv_device *device);
/* Bytes actually consumed in this batch BO */
size_t length;
- /* Last seen surface state block pool bo offset */
- uint32_t last_ss_pool_bo_offset;
-
struct anv_reloc_list relocs;
};
do { \
uint32_t *dw; \
\
- static_assert(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1), "mismatch merge"); \
+ STATIC_ASSERT(ARRAY_SIZE(dwords0) == ARRAY_SIZE(dwords1)); \
dw = anv_batch_emit_dwords((batch), ARRAY_SIZE(dwords0)); \
for (uint32_t i = 0; i < ARRAY_SIZE(dwords0); i++) \
dw[i] = (dwords0)[i] | (dwords1)[i]; \
/* Index in the binding */
uint8_t index;
+
+ /* Input attachment index (relative to the subpass) */
+ uint8_t input_attachment_index;
};
struct anv_pipeline_layout {
* The clear value is valid only if there exists a pending clear.
*/
struct anv_attachment_state {
+ enum isl_aux_usage aux_usage;
+ enum isl_aux_usage input_aux_usage;
+ struct anv_state color_rt_state;
+ struct anv_state input_att_state;
+
VkImageAspectFlags pending_clear_aspects;
+ bool fast_clear;
VkClearValue clear_value;
+ bool clear_color_is_zero_one;
};
/** State required while building cmd buffer */
*/
struct anv_attachment_state * attachments;
+ /**
+ * Surface states for color render targets. These are stored in a single
+ * flat array. For depth-stencil attachments, the surface state is simply
+ * left blank.
+ */
+ struct anv_state render_pass_states;
+
+ /**
+ * A null surface state of the right size to match the framebuffer. This
+ * is one of the states in render_pass_states.
+ */
+ struct anv_state null_surface_state;
+
struct {
struct anv_buffer * index_buffer;
uint32_t index_type; /**< 3DSTATE_INDEX_BUFFER.IndexFormat */
*/
struct u_vector bt_blocks;
uint32_t bt_next;
- struct anv_reloc_list surface_relocs;
- /* Information needed for execbuf
- *
- * These fields are generated by anv_cmd_buffer_prepare_execbuf().
- */
- struct {
- struct drm_i915_gem_execbuffer2 execbuf;
-
- struct drm_i915_gem_exec_object2 * objects;
- uint32_t bo_count;
- struct anv_bo ** bos;
-
- /* Allocated length of the 'objects' and 'bos' arrays */
- uint32_t array_length;
- } execbuf2;
+ struct anv_reloc_list surface_relocs;
+ /** Last seen surface state block pool center bo offset */
+ uint32_t last_ss_pool_center;
/* Serial for tracking buffer completion */
uint32_t serial;
bool depth_clamp_enable);
void gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer *cmd_buffer);
-void anv_cmd_state_setup_attachments(struct anv_cmd_buffer *cmd_buffer,
- const VkRenderPassBeginInfo *info);
+void anv_cmd_buffer_setup_attachments(struct anv_cmd_buffer *cmd_buffer,
+ struct anv_render_pass *pass,
+ struct anv_framebuffer *framebuffer,
+ const VkClearValue *clear_values);
+
+void anv_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer *cmd_buffer);
struct anv_state
anv_cmd_buffer_push_constants(struct anv_cmd_buffer *cmd_buffer,
const struct anv_image_view *
anv_cmd_buffer_get_depth_stencil_view(const struct anv_cmd_buffer *cmd_buffer);
+struct anv_state
+anv_cmd_buffer_alloc_blorp_binding_table(struct anv_cmd_buffer *cmd_buffer,
+ uint32_t num_entries,
+ uint32_t *state_offset);
+
void anv_cmd_buffer_dump(struct anv_cmd_buffer *cmd_buffer);
+enum anv_fence_state {
+ /** Indicates that this is a new (or newly reset fence) */
+ ANV_FENCE_STATE_RESET,
+
+ /** Indicates that this fence has been submitted to the GPU but is still
+ * (as far as we know) in use by the GPU.
+ */
+ ANV_FENCE_STATE_SUBMITTED,
+
+ ANV_FENCE_STATE_SIGNALED,
+};
+
struct anv_fence {
struct anv_bo bo;
struct drm_i915_gem_execbuffer2 execbuf;
struct drm_i915_gem_exec_object2 exec2_objects[1];
- bool ready;
+ enum anv_fence_state state;
};
struct anv_event {
VkShaderStageFlags active_stages;
struct anv_state blend_state;
- uint32_t vs_simd8;
- uint32_t vs_vec4;
- uint32_t ps_ksp0;
- uint32_t gs_kernel;
- uint32_t cs_simd;
uint32_t vb_used;
uint32_t binding_stride[MAX_VBS];
struct {
uint32_t wm_depth_stencil[4];
} gen9;
+
+ uint32_t interface_descriptor_data[8];
};
static inline bool
struct {
struct anv_surface depth_surface;
- struct anv_surface hiz_surface;
struct anv_surface stencil_surface;
};
};
+
+ /** The aux usage for this surface when outside a render pass */
+ enum isl_aux_usage aux_usage;
+
+ struct anv_surface aux_surface;
};
static inline uint32_t
VkFormat vk_format;
VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
- /** RENDER_SURFACE_STATE when using image as a color render target. */
- struct anv_state color_rt_surface_state;
-
/** RENDER_SURFACE_STATE when using image as a sampler surface. */
struct anv_state sampler_surface_state;
static inline bool
anv_image_has_hiz(const struct anv_image *image)
{
- /* We must check the aspect because anv_image::hiz_surface belongs to
- * a union.
+ /* We must check the aspect because anv_image::aux_surface may be used for
+ * any type of auxiliary surface, not just HiZ.
*/
return (image->aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
- image->hiz_surface.isl.size > 0;
+ image->aux_surface.isl.size > 0;
}
struct anv_buffer_view {
uint32_t * resolve_attachments;
uint32_t depth_stencil_attachment;
+ /** Subpass has a depth/stencil self-dependency */
+ bool has_ds_self_dep;
+
/** Subpass has at least one resolve attachment */
bool has_resolve;
};
+enum anv_subpass_usage {
+ ANV_SUBPASS_USAGE_DRAW = (1 << 0),
+ ANV_SUBPASS_USAGE_INPUT = (1 << 1),
+ ANV_SUBPASS_USAGE_RESOLVE_SRC = (1 << 2),
+ ANV_SUBPASS_USAGE_RESOLVE_DST = (1 << 3),
+};
+
struct anv_render_pass_attachment {
VkFormat format;
uint32_t samples;
+ VkImageUsageFlags usage;
VkAttachmentLoadOp load_op;
VkAttachmentStoreOp store_op;
VkAttachmentLoadOp stencil_load_op;
+
+ /* An array, indexed by subpass id, of how the attachment will be used. */
+ enum anv_subpass_usage * subpass_usage;
};
struct anv_render_pass {
uint32_t attachment_count;
uint32_t subpass_count;
uint32_t * subpass_attachments;
+ enum anv_subpass_usage * subpass_usages;
struct anv_render_pass_attachment * attachments;
struct anv_subpass subpasses[0];
};
projects / mesa.git / blobdiff