anv: Use a proper end-of-pipe sync instead of just CS stall

[mesa.git] / src / intel / vulkan / anv_private.h

diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index 0072bd8422d17d1843cc904e355a917fc8063297..288d6ece12e4fc3843183f6700131663a18f2a6c 100644 (file)
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -2251,13 +2251,14 @@ enum anv_pipe_bits {
    ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT    = (1 << 12),
    ANV_PIPE_DEPTH_STALL_BIT                  = (1 << 13),
    ANV_PIPE_CS_STALL_BIT                     = (1 << 20),
+   ANV_PIPE_END_OF_PIPE_SYNC_BIT             = (1 << 21),
 
    /* This bit does not exist directly in PIPE_CONTROL.  Instead it means that
     * a flush has happened but not a CS stall.  The next time we do any sort
     * of invalidation we need to insert a CS stall at that time.  Otherwise,
     * we would have to CS stall on every flush which could be bad.
     */
-   ANV_PIPE_NEEDS_CS_STALL_BIT               = (1 << 21),
+   ANV_PIPE_NEEDS_END_OF_PIPE_SYNC_BIT       = (1 << 22),
 
    /* This bit does not exist directly in PIPE_CONTROL. It means that render
     * target operations related to transfer commands with VkBuffer as
@@ -2265,19 +2266,19 @@ enum anv_pipe_bits {
     * streamer might need to be aware of this to trigger the appropriate stall
     * before they can proceed with the copy.
     */
-   ANV_PIPE_RENDER_TARGET_BUFFER_WRITES      = (1 << 22),
+   ANV_PIPE_RENDER_TARGET_BUFFER_WRITES      = (1 << 23),
 
    /* This bit does not exist directly in PIPE_CONTROL. It means that Gen12
     * AUX-TT data has changed and we need to invalidate AUX-TT data.  This is
     * done by writing the AUX-TT register.
     */
-   ANV_PIPE_AUX_TABLE_INVALIDATE_BIT         = (1 << 23),
+   ANV_PIPE_AUX_TABLE_INVALIDATE_BIT         = (1 << 24),
 
    /* This bit does not exist directly in PIPE_CONTROL. It means that a
     * PIPE_CONTROL with a post-sync operation will follow. This is used to
     * implement a workaround for Gen9.
     */
-   ANV_PIPE_POST_SYNC_BIT                    = (1 << 24),
+   ANV_PIPE_POST_SYNC_BIT                    = (1 << 25),
 };
 
 #define ANV_PIPE_FLUSH_BITS ( \