#endif
#include "brw_device_info.h"
+#include "brw_compiler.h"
#include "util/macros.h"
#include "util/list.h"
uint32_t total_size;
uint32_t table_size;
uint32_t kernel_count;
- uint32_t *table;
+ uint32_t * hash_table;
};
+struct anv_pipeline_bind_map;
+
void anv_pipeline_cache_init(struct anv_pipeline_cache *cache,
struct anv_device *device);
void anv_pipeline_cache_finish(struct anv_pipeline_cache *cache);
uint32_t anv_pipeline_cache_search(struct anv_pipeline_cache *cache,
- const unsigned char *sha1, void *prog_data);
+ const unsigned char *sha1,
+ const struct brw_stage_prog_data **prog_data,
+ struct anv_pipeline_bind_map *map);
uint32_t anv_pipeline_cache_upload_kernel(struct anv_pipeline_cache *cache,
const unsigned char *sha1,
const void *kernel,
size_t kernel_size,
- const void *prog_data,
- size_t prog_data_size);
+ const struct brw_stage_prog_data **prog_data,
+ size_t prog_data_size,
+ struct anv_pipeline_bind_map *map);
struct anv_device {
VK_LOADER_DATA _loader_data;
struct anv_block_pool scratch_block_pool;
+ uint32_t default_mocs;
+
pthread_mutex_t mutex;
};
.L3CacheabilityControlL3CC = 1, \
}
-#define GEN8_MOCS { \
- .MemoryTypeLLCeLLCCacheabilityControl = WB, \
- .TargetCache = L3DefertoPATforLLCeLLCselection, \
- .AgeforQUADLRU = 0 \
+#define GEN8_MOCS (struct GEN8_MEMORY_OBJECT_CONTROL_STATE) { \
+ .MemoryTypeLLCeLLCCacheabilityControl = WB, \
+ .TargetCache = L3DefertoPATforLLCeLLCselection, \
+ .AgeforQUADLRU = 0 \
}
/* Skylake: MOCS is now an index into an array of 62 different caching
* configurations programmed by the kernel.
*/
-#define GEN9_MOCS { \
- /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
- .IndextoMOCSTables = 2 \
+#define GEN9_MOCS (struct GEN9_MEMORY_OBJECT_CONTROL_STATE) { \
+ /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */ \
+ .IndextoMOCSTables = 2 \
}
#define GEN9_MOCS_PTE { \
struct anv_descriptor_set {
const struct anv_descriptor_set_layout *layout;
+ uint32_t size;
uint32_t buffer_count;
struct anv_buffer_view *buffer_views;
struct anv_descriptor descriptors[0];
};
+struct anv_descriptor_pool {
+ uint32_t size;
+ uint32_t next;
+ uint32_t free_list;
+
+ struct anv_state_stream surface_state_stream;
+ void *surface_state_free_list;
+
+ char data[0];
+};
+
VkResult
anv_descriptor_set_create(struct anv_device *device,
+ struct anv_descriptor_pool *pool,
const struct anv_descriptor_set_layout *layout,
struct anv_descriptor_set **out_set);
void
anv_descriptor_set_destroy(struct anv_device *device,
+ struct anv_descriptor_pool *pool,
struct anv_descriptor_set *set);
+#define ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS UINT16_MAX
+
struct anv_pipeline_binding {
- /* The descriptor set this surface corresponds to */
+ /* The descriptor set this surface corresponds to. The special value of
+ * ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS indicates that the offset refers
+ * to a color attachment and not a regular descriptor.
+ */
uint16_t set;
- /* Offset into the descriptor set */
+ /* Offset into the descriptor set or attachment list. */
uint16_t offset;
};
void anv_cmd_state_setup_attachments(struct anv_cmd_buffer *cmd_buffer,
const VkRenderPassBeginInfo *info);
+struct anv_state
+gen7_cmd_buffer_alloc_null_surface_state(struct anv_cmd_buffer *cmd_buffer,
+ struct anv_framebuffer *fb);
+struct anv_state
+gen75_cmd_buffer_alloc_null_surface_state(struct anv_cmd_buffer *cmd_buffer,
+ struct anv_framebuffer *fb);
+struct anv_state
+gen8_cmd_buffer_alloc_null_surface_state(struct anv_cmd_buffer *cmd_buffer,
+ struct anv_framebuffer *fb);
+struct anv_state
+gen9_cmd_buffer_alloc_null_surface_state(struct anv_cmd_buffer *cmd_buffer,
+ struct anv_framebuffer *fb);
+
void gen7_cmd_buffer_set_subpass(struct anv_cmd_buffer *cmd_buffer,
struct anv_subpass *subpass);
void gen75_cmd_buffer_set_subpass(struct anv_cmd_buffer *cmd_buffer,
uint32_t surface_count;
uint32_t sampler_count;
uint32_t image_count;
+ uint32_t attachment_count;
struct anv_pipeline_binding * surface_to_descriptor;
struct anv_pipeline_binding * sampler_to_descriptor;
+ uint32_t * surface_to_attachment;
};
struct anv_pipeline {
bool use_repclear;
- struct brw_vs_prog_data vs_prog_data;
- struct brw_wm_prog_data wm_prog_data;
- struct brw_gs_prog_data gs_prog_data;
- struct brw_cs_prog_data cs_prog_data;
- bool writes_point_size;
- struct brw_stage_prog_data * prog_data[MESA_SHADER_STAGES];
+ const struct brw_stage_prog_data * prog_data[MESA_SHADER_STAGES];
uint32_t scratch_start[MESA_SHADER_STAGES];
uint32_t total_scratch;
struct {
- uint32_t vs_start;
- uint32_t vs_size;
- uint32_t nr_vs_entries;
- uint32_t gs_start;
- uint32_t gs_size;
- uint32_t nr_gs_entries;
+ uint8_t push_size[MESA_SHADER_FRAGMENT + 1];
+ uint32_t start[MESA_SHADER_GEOMETRY + 1];
+ uint32_t size[MESA_SHADER_GEOMETRY + 1];
+ uint32_t entries[MESA_SHADER_GEOMETRY + 1];
} urb;
VkShaderStageFlags active_stages;
} gen9;
};
+static inline const struct brw_vs_prog_data *
+get_vs_prog_data(struct anv_pipeline *pipeline)
+{
+ return (const struct brw_vs_prog_data *) pipeline->prog_data[MESA_SHADER_VERTEX];
+}
+
+static inline const struct brw_gs_prog_data *
+get_gs_prog_data(struct anv_pipeline *pipeline)
+{
+ return (const struct brw_gs_prog_data *) pipeline->prog_data[MESA_SHADER_GEOMETRY];
+}
+
+static inline const struct brw_wm_prog_data *
+get_wm_prog_data(struct anv_pipeline *pipeline)
+{
+ return (const struct brw_wm_prog_data *) pipeline->prog_data[MESA_SHADER_FRAGMENT];
+}
+
+static inline const struct brw_cs_prog_data *
+get_cs_prog_data(struct anv_pipeline *pipeline)
+{
+ return (const struct brw_cs_prog_data *) pipeline->prog_data[MESA_SHADER_COMPUTE];
+}
+
struct anv_graphics_pipeline_create_info {
/**
* If non-negative, overrides the color attachment count of the pipeline's
};
};
+static inline uint32_t
+anv_get_layerCount(const struct anv_image *image,
+ const VkImageSubresourceRange *range)
+{
+ return range->layerCount == VK_REMAINING_ARRAY_LAYERS ?
+ image->array_size - range->baseArrayLayer : range->layerCount;
+}
+
+static inline uint32_t
+anv_get_levelCount(const struct anv_image *image,
+ const VkImageSubresourceRange *range)
+{
+ return range->levelCount == VK_REMAINING_MIP_LEVELS ?
+ image->levels - range->baseMipLevel : range->levelCount;
+}
+
+
struct anv_image_view {
const struct anv_image *image; /**< VkImageViewCreateInfo::image */
struct anv_bo *bo;
VkImageAspectFlags aspect_mask;
VkFormat vk_format;
- VkComponentMapping swizzle;
- enum isl_format format;
uint32_t base_layer;
uint32_t base_mip;
- VkExtent3D level_0_extent; /**< Extent of ::image's level 0 adjusted for ::vk_format. */
VkExtent3D extent; /**< Extent of VkImageViewCreateInfo::baseMipLevel. */
/** RENDER_SURFACE_STATE when using image as a color render target. */
/** RENDER_SURFACE_STATE when using image as a storage image. */
struct anv_state storage_surface_state;
+
+ struct brw_image_param storage_image_param;
};
struct anv_image_create_info {
struct anv_device *device,
const VkImageViewCreateInfo* pCreateInfo,
struct anv_cmd_buffer *cmd_buffer,
- uint32_t offset);
+ uint32_t offset,
+ VkImageUsageFlags usage_mask);
void
anv_fill_image_surface_state(struct anv_device *device, struct anv_state state,
struct anv_state surface_state;
struct anv_state storage_surface_state;
+
+ struct brw_image_param storage_image_param;
};
const struct anv_format *
ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_cmd_pool, VkCommandPool)
ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer, VkBuffer)
ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_buffer_view, VkBufferView)
+ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_pool, VkDescriptorPool)
ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set, VkDescriptorSet)
ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_descriptor_set_layout, VkDescriptorSetLayout)
ANV_DEFINE_NONDISP_HANDLE_CASTS(anv_device_memory, VkDeviceMemory)
projects / mesa.git / blobdiff