anv_foreach_stage(s, stages) {
if (cmd_buffer->state.samplers[s].alloc_size > 0) {
- anv_batch_emit_blk(&cmd_buffer->batch,
- GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS), ssp) {
+ anv_batch_emit(&cmd_buffer->batch,
+ GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS), ssp) {
ssp._3DCommandSubOpcode = sampler_state_opcodes[s];
ssp.PointertoVSSamplerState = cmd_buffer->state.samplers[s].offset;
}
/* Always emit binding table pointers if we're asked to, since on SKL
* this is what flushes push constants. */
- anv_batch_emit_blk(&cmd_buffer->batch,
- GENX(3DSTATE_BINDING_TABLE_POINTERS_VS), btp) {
+ anv_batch_emit(&cmd_buffer->batch,
+ GENX(3DSTATE_BINDING_TABLE_POINTERS_VS), btp) {
btp._3DCommandSubOpcode = binding_table_opcodes[s];
btp.PointertoVSBindingTable = cmd_buffer->state.binding_tables[s].offset;
}
}
}
- anv_batch_emit_blk(&cmd_buffer->batch,
- GEN7_3DSTATE_SCISSOR_STATE_POINTERS, ssp) {
+ anv_batch_emit(&cmd_buffer->batch,
+ GEN7_3DSTATE_SCISSOR_STATE_POINTERS, ssp) {
ssp.ScissorRectPointer = scissor_state.offset;
}
unsigned push_constant_regs = reg_aligned_constant_size / 32;
if (push_state.alloc_size) {
- anv_batch_emit_blk(&cmd_buffer->batch, GENX(MEDIA_CURBE_LOAD), curbe) {
+ anv_batch_emit(&cmd_buffer->batch, GENX(MEDIA_CURBE_LOAD), curbe) {
curbe.CURBETotalDataLength = push_state.alloc_size;
curbe.CURBEDataStartAddress = push_state.offset;
}
pipeline->cs_thread_width_max);
const uint32_t size = GENX(INTERFACE_DESCRIPTOR_DATA_length) * sizeof(uint32_t);
- anv_batch_emit_blk(&cmd_buffer->batch,
- GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD), idl) {
+ anv_batch_emit(&cmd_buffer->batch,
+ GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD), idl) {
idl.InterfaceDescriptorTotalLength = size;
idl.InterfaceDescriptorDataStartAddress = state.offset;
}
return VK_SUCCESS;
}
-void
-genX(cmd_buffer_config_l3)(struct anv_cmd_buffer *cmd_buffer, bool enable_slm)
-{
- /* References for GL state:
- *
- * - commits e307cfa..228d5a3
- * - src/mesa/drivers/dri/i965/gen7_l3_state.c
- */
-
- uint32_t l3cr2_slm, l3cr2_noslm;
- anv_pack_struct(&l3cr2_noslm, GENX(L3CNTLREG2),
- .URBAllocation = 24,
- .ROAllocation = 0,
- .DCAllocation = 16);
- anv_pack_struct(&l3cr2_slm, GENX(L3CNTLREG2),
- .SLMEnable = 1,
- .URBAllocation = 16,
- .URBLowBandwidth = 1,
- .ROAllocation = 0,
- .DCAllocation = 8);
- const uint32_t l3cr2_val = enable_slm ? l3cr2_slm : l3cr2_noslm;
- bool changed = cmd_buffer->state.current_l3_config != l3cr2_val;
-
- if (changed) {
- /* According to the hardware docs, the L3 partitioning can only be
- * changed while the pipeline is completely drained and the caches are
- * flushed, which involves a first PIPE_CONTROL flush which stalls the
- * pipeline...
- */
- anv_batch_emit_blk(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
- pc.DCFlushEnable = true;
- pc.CommandStreamerStallEnable = true;
- pc.PostSyncOperation = NoWrite;
- }
-
- /* ...followed by a second pipelined PIPE_CONTROL that initiates
- * invalidation of the relevant caches. Note that because RO
- * invalidation happens at the top of the pipeline (i.e. right away as
- * the PIPE_CONTROL command is processed by the CS) we cannot combine it
- * with the previous stalling flush as the hardware documentation
- * suggests, because that would cause the CS to stall on previous
- * rendering *after* RO invalidation and wouldn't prevent the RO caches
- * from being polluted by concurrent rendering before the stall
- * completes. This intentionally doesn't implement the SKL+ hardware
- * workaround suggesting to enable CS stall on PIPE_CONTROLs with the
- * texture cache invalidation bit set for GPGPU workloads because the
- * previous and subsequent PIPE_CONTROLs already guarantee that there is
- * no concurrent GPGPU kernel execution (see SKL HSD 2132585).
- */
- anv_batch_emit_blk(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
- pc.TextureCacheInvalidationEnable = true;
- pc.ConstantCacheInvalidationEnable = true;
- pc.InstructionCacheInvalidateEnable = true;
- pc.StateCacheInvalidationEnable = true;
- pc.PostSyncOperation = NoWrite;
- }
-
- /* Now send a third stalling flush to make sure that invalidation is
- * complete when the L3 configuration registers are modified.
- */
- anv_batch_emit_blk(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
- pc.DCFlushEnable = true;
- pc.CommandStreamerStallEnable = true;
- pc.PostSyncOperation = NoWrite;
- }
-
- anv_finishme("write GEN7_L3SQCREG1");
- anv_batch_emit_blk(&cmd_buffer->batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
- lri.RegisterOffset = GENX(L3CNTLREG2_num);
- lri.DataDWord = l3cr2_val;
- }
-
- uint32_t l3cr3_slm, l3cr3_noslm;
- anv_pack_struct(&l3cr3_noslm, GENX(L3CNTLREG3),
- .ISAllocation = 8,
- .CAllocation = 4,
- .TAllocation = 8);
- anv_pack_struct(&l3cr3_slm, GENX(L3CNTLREG3),
- .ISAllocation = 8,
- .CAllocation = 8,
- .TAllocation = 8);
- const uint32_t l3cr3_val = enable_slm ? l3cr3_slm : l3cr3_noslm;
- anv_batch_emit_blk(&cmd_buffer->batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
- lri.RegisterOffset = GENX(L3CNTLREG3_num);
- lri.DataDWord = l3cr3_val;
- }
-
- cmd_buffer->state.current_l3_config = l3cr2_val;
- }
-}
-
void
genX(cmd_buffer_flush_compute_state)(struct anv_cmd_buffer *cmd_buffer)
{
struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline;
- const struct brw_cs_prog_data *cs_prog_data = get_cs_prog_data(pipeline);
- VkResult result;
+ MAYBE_UNUSED VkResult result;
assert(pipeline->active_stages == VK_SHADER_STAGE_COMPUTE_BIT);
- bool needs_slm = cs_prog_data->base.total_shared > 0;
- genX(cmd_buffer_config_l3)(cmd_buffer, needs_slm);
+ genX(cmd_buffer_config_l3)(cmd_buffer, pipeline);
genX(flush_pipeline_select_gpgpu)(cmd_buffer);
const struct anv_image_view *iview =
anv_cmd_buffer_get_depth_stencil_view(cmd_buffer);
const struct anv_image *image = iview ? iview->image : NULL;
- const struct anv_format *anv_format =
- iview ? anv_format_for_vk_format(iview->vk_format) : NULL;
- const bool has_depth = iview && anv_format->has_depth;
+ const bool has_depth =
+ image && (image->aspects & VK_IMAGE_ASPECT_DEPTH_BIT);
const uint32_t depth_format = has_depth ?
isl_surf_get_depth_format(&cmd_buffer->device->isl_dev,
&image->depth_surface.isl) : D16_UNORM;
if (!cmd_buffer->device->info.has_llc)
anv_state_clflush(cc_state);
- anv_batch_emit_blk(&cmd_buffer->batch,
- GENX(3DSTATE_CC_STATE_POINTERS), ccp) {
+ anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CC_STATE_POINTERS), ccp) {
ccp.ColorCalcStatePointer = cc_state.offset;
}
}
pipeline->gen7.depth_stencil_state,
GENX(DEPTH_STENCIL_STATE_length), 64);
- anv_batch_emit_blk(&cmd_buffer->batch,
- GENX(3DSTATE_DEPTH_STENCIL_STATE_POINTERS), dsp) {
+ anv_batch_emit(&cmd_buffer->batch,
+ GENX(3DSTATE_DEPTH_STENCIL_STATE_POINTERS), dsp) {
dsp.PointertoDEPTH_STENCIL_STATE = ds_state.offset;
}
}
uint32_t offset = cmd_buffer->state.gen7.index_offset;
#if GEN_IS_HASWELL
- anv_batch_emit_blk(&cmd_buffer->batch, GEN75_3DSTATE_VF, vf) {
+ anv_batch_emit(&cmd_buffer->batch, GEN75_3DSTATE_VF, vf) {
vf.IndexedDrawCutIndexEnable = pipeline->primitive_restart;
vf.CutIndex = cmd_buffer->state.restart_index;
}
#endif
- anv_batch_emit_blk(&cmd_buffer->batch, GENX(3DSTATE_INDEX_BUFFER), ib) {
+ anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_INDEX_BUFFER), ib) {
#if !GEN_IS_HASWELL
ib.CutIndexEnable = pipeline->primitive_restart;
#endif
const VkImageMemoryBarrier* pImageMemoryBarriers)
{
stub();
+
+ genX(CmdPipelineBarrier)(commandBuffer, srcStageMask, destStageMask,
+ false, /* byRegion */
+ memoryBarrierCount, pMemoryBarriers,
+ bufferMemoryBarrierCount, pBufferMemoryBarriers,
+ imageMemoryBarrierCount, pImageMemoryBarriers);
}
projects / mesa.git / blobdiff