anv/allocator: Move the alignment assert for the pointer free list

[mesa.git] / src / intel / vulkan / gen8_pipeline.c

diff --git a/src/intel/vulkan/gen8_pipeline.c b/src/intel/vulkan/gen8_pipeline.c
index e8a067851cc6532ab86614231d20ca5cfe3cc5e4..10dd6457fbc99dc9079c8d2e83f24bc38cda2116 100644 (file)
--- a/src/intel/vulkan/gen8_pipeline.c
+++ b/src/intel/vulkan/gen8_pipeline.c
@@ -60,7 +60,7 @@ emit_rs_state(struct anv_pipeline *pipeline,
       .TriangleStripListProvokingVertexSelect = 0,
       .LineStripListProvokingVertexSelect = 0,
       .TriangleFanProvokingVertexSelect = 1,
-      .PointWidthSource = pipeline->writes_point_size ? Vertex : State,
+      .PointWidthSource = Vertex,
       .PointWidth = 1.0,
    };
 
@@ -238,6 +238,14 @@ emit_ds_state(struct anv_pipeline *pipeline,
       .BackfaceStencilTestFunction = vk_to_gen_compare_op[info->back.compareOp],
    };
 
+   /* From the Broadwell PRM:
+    *
+    *    "If Depth_Test_Enable = 1 AND Depth_Test_func = EQUAL, the
+    *    Depth_Write_Enable must be set to 0."
+    */
+   if (info->depthTestEnable && info->depthCompareOp == VK_COMPARE_OP_EQUAL)
+      wm_depth_stencil.DepthBufferWriteEnable = false;
+
    GENX(3DSTATE_WM_DEPTH_STENCIL_pack)(NULL, dw, &wm_depth_stencil);
 }
 
@@ -325,6 +333,7 @@ genX(graphics_pipeline_create)(
 
    emit_urb_setup(pipeline);
 
+   const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
    anv_batch_emit(&pipeline->batch, GENX(3DSTATE_CLIP),
                   .ClipEnable = true,
                   .EarlyCullEnable = true,
@@ -335,8 +344,8 @@ genX(graphics_pipeline_create)(
                      pCreateInfo->pRasterizationState->rasterizerDiscardEnable ?
                      REJECT_ALL : NORMAL,
 
-                  .NonPerspectiveBarycentricEnable =
-                     (pipeline->wm_prog_data.barycentric_interp_modes & 0x38) != 0,
+                  .NonPerspectiveBarycentricEnable = wm_prog_data ?
+                     (wm_prog_data->barycentric_interp_modes & 0x38) != 0 : 0,
 
                   .TriangleStripListProvokingVertexSelect = 0,
                   .LineStripListProvokingVertexSelect = 0,
@@ -355,15 +364,15 @@ genX(graphics_pipeline_create)(
                   .PointRasterizationRule = RASTRULE_UPPER_RIGHT,
                   .BarycentricInterpolationMode =
                      pipeline->ps_ksp0 == NO_KERNEL ?
-                     0 : pipeline->wm_prog_data.barycentric_interp_modes);
-
-   const struct brw_gs_prog_data *gs_prog_data = &pipeline->gs_prog_data;
-   offset = 1;
-   length = (gs_prog_data->base.vue_map.num_slots + 1) / 2 - offset;
+                     0 : wm_prog_data->barycentric_interp_modes);
 
-   if (pipeline->gs_kernel == NO_KERNEL)
+   if (pipeline->gs_kernel == NO_KERNEL) {
       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_GS), .Enable = false);
-   else
+   } else {
+      const struct brw_gs_prog_data *gs_prog_data = get_gs_prog_data(pipeline);
+      offset = 1;
+      length = (gs_prog_data->base.vue_map.num_slots + 1) / 2 - offset;
+
       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_GS),
                      .SingleProgramFlow = false,
                      .KernelStartPointer = pipeline->gs_kernel,
@@ -404,11 +413,12 @@ genX(graphics_pipeline_create)(
 
                      .VertexURBEntryOutputReadOffset = offset,
                      .VertexURBEntryOutputLength = length);
+   }
 
-   const struct brw_vue_prog_data *vue_prog_data = &pipeline->vs_prog_data.base;
+   const struct brw_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
    /* Skip the VUE header and position slots */
    offset = 1;
-   length = (vue_prog_data->vue_map.num_slots + 1) / 2 - offset;
+   length = (vs_prog_data->base.vue_map.num_slots + 1) / 2 - offset;
 
    uint32_t vs_start = pipeline->vs_simd8 != NO_KERNEL ? pipeline->vs_simd8 :
                                                          pipeline->vs_vec4;
@@ -427,7 +437,7 @@ genX(graphics_pipeline_create)(
                      .VectorMaskEnable = false,
                      .SamplerCount = 0,
                      .BindingTableEntryCount =
-                     vue_prog_data->base.binding_table.size_bytes / 4,
+                        vs_prog_data->base.base.binding_table.size_bytes / 4,
                      .ThreadDispatchPriority = false,
                      .FloatingPointMode = IEEE754,
                      .IllegalOpcodeExceptionEnable = false,
@@ -435,11 +445,11 @@ genX(graphics_pipeline_create)(
                      .SoftwareExceptionEnable = false,
 
                      .ScratchSpaceBasePointer = pipeline->scratch_start[MESA_SHADER_VERTEX],
-                     .PerThreadScratchSpace = scratch_space(&vue_prog_data->base),
+                     .PerThreadScratchSpace = scratch_space(&vs_prog_data->base.base),
 
                      .DispatchGRFStartRegisterForURBData =
-                     vue_prog_data->base.dispatch_grf_start_reg,
-                     .VertexURBEntryReadLength = vue_prog_data->urb_read_length,
+                        vs_prog_data->base.base.dispatch_grf_start_reg,
+                     .VertexURBEntryReadLength = vs_prog_data->base.urb_read_length,
                      .VertexURBEntryReadOffset = 0,
 
                      .MaximumNumberofThreads = device->info.max_vs_threads - 1,
@@ -453,8 +463,6 @@ genX(graphics_pipeline_create)(
                      .UserClipDistanceClipTestEnableBitmask = 0,
                      .UserClipDistanceCullTestEnableBitmask = 0);
 
-   const struct brw_wm_prog_data *wm_prog_data = &pipeline->wm_prog_data;
-
    const int num_thread_bias = GEN_GEN == 8 ? 2 : 1;
    if (pipeline->ps_ksp0 == NO_KERNEL) {
       anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS));