struct blorp_address address, uint32_t delta)
{
struct anv_cmd_buffer *cmd_buffer = batch->driver_batch;
- anv_reloc_list_add(&cmd_buffer->surface_relocs, &cmd_buffer->pool->alloc,
- ss_offset, address.buffer, address.offset + delta);
+ uint64_t address_u64 = 0;
+ VkResult result =
+ anv_reloc_list_add(&cmd_buffer->surface_relocs, &cmd_buffer->pool->alloc,
+ ss_offset, address.buffer, address.offset + delta,
+ &address_u64);
+ if (result != VK_SUCCESS)
+ anv_batch_set_error(&cmd_buffer->batch, result);
+
+ void *dest = anv_block_pool_map(
+ &cmd_buffer->device->surface_state_pool.block_pool, ss_offset, 8);
+ write_reloc(cmd_buffer->device, dest, address_u64, false);
+}
+
+static uint64_t
+blorp_get_surface_address(struct blorp_batch *blorp_batch,
+ struct blorp_address address)
+{
+ /* We'll let blorp_surface_reloc write the address. */
+ return 0ull;
}
+#if GEN_GEN >= 7 && GEN_GEN < 10
+static struct blorp_address
+blorp_get_surface_base_address(struct blorp_batch *batch)
+{
+ struct anv_cmd_buffer *cmd_buffer = batch->driver_batch;
+ return (struct blorp_address) {
+ .buffer = cmd_buffer->device->surface_state_pool.block_pool.bo,
+ .offset = 0,
+ };
+}
+#endif
+
static void *
blorp_alloc_dynamic_state(struct blorp_batch *batch,
- enum aub_state_struct_type type,
uint32_t size,
uint32_t alignment,
uint32_t *offset)
struct anv_cmd_buffer *cmd_buffer = batch->driver_batch;
uint32_t state_offset;
- struct anv_state bt_state =
- anv_cmd_buffer_alloc_binding_table(cmd_buffer, num_entries,
- &state_offset);
- if (bt_state.map == NULL) {
- /* We ran out of space. Grab a new binding table block. */
- VkResult result = anv_cmd_buffer_new_binding_table_block(cmd_buffer);
- assert(result == VK_SUCCESS);
-
- /* Re-emit state base addresses so we get the new surface state base
- * address before we start emitting binding tables etc.
- */
- anv_cmd_buffer_emit_state_base_address(cmd_buffer);
-
- bt_state = anv_cmd_buffer_alloc_binding_table(cmd_buffer, num_entries,
- &state_offset);
- assert(bt_state.map != NULL);
- }
+ struct anv_state bt_state;
+
+ VkResult result =
+ anv_cmd_buffer_alloc_blorp_binding_table(cmd_buffer, num_entries,
+ &state_offset, &bt_state);
+ if (result != VK_SUCCESS)
+ return;
uint32_t *bt_map = bt_state.map;
*bt_offset = bt_state.offset;
{
struct anv_cmd_buffer *cmd_buffer = batch->driver_batch;
struct anv_state vb_state =
- anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, size, 16);
+ anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, size, 64);
*addr = (struct blorp_address) {
- .buffer = &cmd_buffer->device->dynamic_state_block_pool.bo,
+ .buffer = cmd_buffer->device->dynamic_state_pool.block_pool.bo,
.offset = vb_state.offset,
+ .mocs = cmd_buffer->device->isl_dev.mocs.internal,
};
return vb_state.map;
}
static void
-blorp_emit_urb_config(struct blorp_batch *batch, unsigned vs_entry_size)
+blorp_vf_invalidate_for_vb_48b_transitions(struct blorp_batch *batch,
+ const struct blorp_address *addrs,
+ uint32_t *sizes,
+ unsigned num_vbs)
+{
+ struct anv_cmd_buffer *cmd_buffer = batch->driver_batch;
+
+ for (unsigned i = 0; i < num_vbs; i++) {
+ struct anv_address anv_addr = {
+ .bo = addrs[i].buffer,
+ .offset = addrs[i].offset,
+ };
+ genX(cmd_buffer_set_binding_for_gen8_vb_flush)(cmd_buffer,
+ i, anv_addr, sizes[i]);
+ }
+
+ genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
+
+ /* Technically, we should call this *after* 3DPRIMITIVE but it doesn't
+ * really matter for blorp because we never call apply_pipe_flushes after
+ * this point.
+ */
+ genX(cmd_buffer_update_dirty_vbs_for_gen8_vb_flush)(cmd_buffer, SEQUENTIAL,
+ (1 << num_vbs) - 1);
+}
+
+UNUSED static struct blorp_address
+blorp_get_workaround_address(struct blorp_batch *batch)
{
- struct anv_device *device = batch->blorp->driver_ctx;
struct anv_cmd_buffer *cmd_buffer = batch->driver_batch;
- genX(emit_urb_setup)(device, &cmd_buffer->batch,
- VK_SHADER_STAGE_VERTEX_BIT |
- VK_SHADER_STAGE_FRAGMENT_BIT,
- vs_entry_size, 0,
- cmd_buffer->state.current_l3_config);
+ return (struct blorp_address) {
+ .buffer = cmd_buffer->device->workaround_address.bo,
+ .offset = cmd_buffer->device->workaround_address.offset,
+ };
}
-void genX(blorp_exec)(struct blorp_batch *batch,
- const struct blorp_params *params);
+static void
+blorp_flush_range(struct blorp_batch *batch, void *start, size_t size)
+{
+ /* We don't need to flush states anymore, since everything will be snooped.
+ */
+}
+
+static const struct gen_l3_config *
+blorp_get_l3_config(struct blorp_batch *batch)
+{
+ struct anv_cmd_buffer *cmd_buffer = batch->driver_batch;
+ return cmd_buffer->state.current_l3_config;
+}
void
genX(blorp_exec)(struct blorp_batch *batch,
genX(cmd_buffer_config_l3)(cmd_buffer, cfg);
}
- genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
+ const unsigned scale = params->fast_clear_op ? UINT_MAX : 1;
+ genX(cmd_buffer_emit_hashing_mode)(cmd_buffer, params->x1 - params->x0,
+ params->y1 - params->y0, scale);
- if (cmd_buffer->state.current_pipeline != _3D) {
-#if GEN_GEN <= 7
- /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
- * PIPELINE_SELECT [DevBWR+]":
- *
- * Project: DEVSNB+
- *
- * Software must ensure all the write caches are flushed through a
- * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
- * command to invalidate read only caches prior to programming
- * MI_PIPELINE_SELECT command to change the Pipeline Select Mode.
- */
- blorp_emit(batch, GENX(PIPE_CONTROL), pc) {
- pc.RenderTargetCacheFlushEnable = true;
- pc.DepthCacheFlushEnable = true;
- pc.DCFlushEnable = true;
- pc.PostSyncOperation = NoWrite;
- pc.CommandStreamerStallEnable = true;
- }
-
- blorp_emit(batch, GENX(PIPE_CONTROL), pc) {
- pc.TextureCacheInvalidationEnable = true;
- pc.ConstantCacheInvalidationEnable = true;
- pc.StateCacheInvalidationEnable = true;
- pc.InstructionCacheInvalidateEnable = true;
- pc.PostSyncOperation = NoWrite;
- }
+#if GEN_GEN >= 11
+ /* The PIPE_CONTROL command description says:
+ *
+ * "Whenever a Binding Table Index (BTI) used by a Render Taget Message
+ * points to a different RENDER_SURFACE_STATE, SW must issue a Render
+ * Target Cache Flush by enabling this bit. When render target flush
+ * is set due to new association of BTI, PS Scoreboard Stall bit must
+ * be set in this packet."
+ */
+ cmd_buffer->state.pending_pipe_bits |=
+ ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT |
+ ANV_PIPE_STALL_AT_SCOREBOARD_BIT;
#endif
- blorp_emit(batch, GENX(PIPELINE_SELECT), ps) {
-#if GEN_GEN >= 9
- ps.MaskBits = 3;
+#if GEN_GEN == 7
+ /* The MI_LOAD/STORE_REGISTER_MEM commands which BLORP uses to implement
+ * indirect fast-clear colors can cause GPU hangs if we don't stall first.
+ * See genX(cmd_buffer_mi_memcpy) for more details.
+ */
+ if (params->src.clear_color_addr.buffer ||
+ params->dst.clear_color_addr.buffer)
+ cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_CS_STALL_BIT;
#endif
- ps.PipelineSelection = _3D;
- }
- cmd_buffer->state.current_pipeline = _3D;
- }
+ genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
+
+ genX(flush_pipeline_select_3d)(cmd_buffer);
+
+ genX(cmd_buffer_emit_gen7_depth_flush)(cmd_buffer);
+
+ /* BLORP doesn't do anything fancy with depth such as discards, so we want
+ * the PMA fix off. Also, off is always the safe option.
+ */
+ genX(cmd_buffer_enable_pma_fix)(cmd_buffer, false);
blorp_exec(batch, params);
- cmd_buffer->state.vb_dirty = ~0;
- cmd_buffer->state.dirty = ~0;
+#if GEN_GEN >= 11
+ /* The PIPE_CONTROL command description says:
+ *
+ * "Whenever a Binding Table Index (BTI) used by a Render Taget Message
+ * points to a different RENDER_SURFACE_STATE, SW must issue a Render
+ * Target Cache Flush by enabling this bit. When render target flush
+ * is set due to new association of BTI, PS Scoreboard Stall bit must
+ * be set in this packet."
+ */
+ cmd_buffer->state.pending_pipe_bits |=
+ ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT |
+ ANV_PIPE_STALL_AT_SCOREBOARD_BIT;
+#endif
+
+ cmd_buffer->state.gfx.vb_dirty = ~0;
+ cmd_buffer->state.gfx.dirty = ~0;
cmd_buffer->state.push_constants_dirty = ~0;
}