anv: add more swapchain formats

[mesa.git] / src / intel / vulkan / genX_blorp_exec.c

diff --git a/src/intel/vulkan/genX_blorp_exec.c b/src/intel/vulkan/genX_blorp_exec.c
index ac6e73666400e3d5f450014776f4f525f135fec8..2035017ce0e9931a81c3711d451243cda267a81a 100644 (file)
--- a/src/intel/vulkan/genX_blorp_exec.c
+++ b/src/intel/vulkan/genX_blorp_exec.c
@@ -62,8 +62,15 @@ blorp_surface_reloc(struct blorp_batch *batch, uint32_t ss_offset,
                          ss_offset, address.buffer, address.offset + delta);
    if (result != VK_SUCCESS)
       anv_batch_set_error(&cmd_buffer->batch, result);
+
+   void *dest = cmd_buffer->device->surface_state_pool.block_pool.map +
+      ss_offset;
+   uint64_t val = ((struct anv_bo*)address.buffer)->offset + address.offset +
+      delta;
+   write_reloc(cmd_buffer->device, dest, val, false);
 }
 
+#if GEN_GEN >= 7 && GEN_GEN < 10
 static struct blorp_address
 blorp_get_surface_base_address(struct blorp_batch *batch)
 {
@@ -73,6 +80,7 @@ blorp_get_surface_base_address(struct blorp_batch *batch)
       .offset = 0,
    };
 }
+#endif
 
 static void *
 blorp_alloc_dynamic_state(struct blorp_batch *batch,
@@ -150,6 +158,16 @@ blorp_alloc_vertex_buffer(struct blorp_batch *batch, uint32_t size,
    return vb_state.map;
 }
 
+static void
+blorp_vf_invalidate_for_vb_48b_transitions(struct blorp_batch *batch,
+                                           const struct blorp_address *addrs,
+                                           unsigned num_vbs)
+{
+   /* anv forces all vertex buffers into the low 4GB so there are never any
+    * transitions that require a VF invalidation.
+    */
+}
+
 #if GEN_GEN >= 8
 static struct blorp_address
 blorp_get_workaround_page(struct blorp_batch *batch)
@@ -200,6 +218,20 @@ genX(blorp_exec)(struct blorp_batch *batch,
       genX(cmd_buffer_config_l3)(cmd_buffer, cfg);
    }
 
+#if GEN_GEN >= 11
+   /* The PIPE_CONTROL command description says:
+    *
+    *    "Whenever a Binding Table Index (BTI) used by a Render Taget Message
+    *     points to a different RENDER_SURFACE_STATE, SW must issue a Render
+    *     Target Cache Flush by enabling this bit. When render target flush
+    *     is set due to new association of BTI, PS Scoreboard Stall bit must
+    *     be set in this packet."
+    */
+   cmd_buffer->state.pending_pipe_bits |=
+      ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT |
+      ANV_PIPE_STALL_AT_SCOREBOARD_BIT;
+#endif
+
 #if GEN_GEN == 7
    /* The MI_LOAD/STORE_REGISTER_MEM commands which BLORP uses to implement
     * indirect fast-clear colors can cause GPU hangs if we don't stall first.