{
struct anv_device *device = cmd_buffer->device;
-/* XXX: Do we need this on more than just BDW? */
-#if (GEN_GEN >= 8)
/* Emit a render target cache flush.
*
* This isn't documented anywhere in the PRM. However, it seems to be
* clear depth, reset state base address, and then go render stuff.
*/
anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
+ pc.DCFlushEnable = true;
pc.RenderTargetCacheFlushEnable = true;
+ pc.CommandStreamerStallEnable = true;
}
-#endif
anv_batch_emit(&cmd_buffer->batch, GENX(STATE_BASE_ADDRESS), sba) {
sba.GeneralStateBaseAddress = (struct anv_address) { NULL, 0 };
*/
anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
pc.TextureCacheInvalidationEnable = true;
+ pc.ConstantCacheInvalidationEnable = true;
+ pc.StateCacheInvalidationEnable = true;
}
}
render_area.extent.height != iview->extent.height)
att_state->fast_clear = false;
+ if (GEN_GEN <= 7) {
+ /* On gen7, we can't do multi-LOD or multi-layer fast-clears. We
+ * technically can, but it comes with crazy restrictions that we
+ * don't want to deal with now.
+ */
+ if (iview->isl.base_level > 0 ||
+ iview->isl.base_array_layer > 0 ||
+ iview->isl.array_len > 1)
+ att_state->fast_clear = false;
+ }
+
+ /* On Broadwell and earlier, we can only handle 0/1 clear colors */
+ if (GEN_GEN <= 8 && !att_state->clear_color_is_zero_one)
+ att_state->fast_clear = false;
+
if (att_state->fast_clear) {
memcpy(fast_clear_color->u32, att_state->clear_value.color.uint32,
sizeof(fast_clear_color->u32));
att_state->input_aux_usage = ISL_AUX_USAGE_CCS_E;
} else if (att_state->fast_clear) {
att_state->aux_usage = ISL_AUX_USAGE_CCS_D;
- /* From the Sky Lake PRM, RENDER_SURFACE_STATE::AuxiliarySurfaceMode:
- *
- * "If Number of Multisamples is MULTISAMPLECOUNT_1, AUX_CCS_D
- * setting is only allowed if Surface Format supported for Fast
- * Clear. In addition, if the surface is bound to the sampling
- * engine, Surface Format must be supported for Render Target
- * Compression for surfaces bound to the sampling engine."
- *
- * In other words, we can't sample from a fast-cleared image if it
- * doesn't also support color compression.
- */
- att_state->input_aux_usage = ISL_AUX_USAGE_NONE;
+ if (GEN_GEN >= 9) {
+ /* From the Sky Lake PRM, RENDER_SURFACE_STATE::AuxiliarySurfaceMode:
+ *
+ * "If Number of Multisamples is MULTISAMPLECOUNT_1, AUX_CCS_D
+ * setting is only allowed if Surface Format supported for Fast
+ * Clear. In addition, if the surface is bound to the sampling
+ * engine, Surface Format must be supported for Render Target
+ * Compression for surfaces bound to the sampling engine."
+ *
+ * In other words, we can't sample from a fast-cleared image if it
+ * doesn't also support color compression.
+ */
+ att_state->input_aux_usage = ISL_AUX_USAGE_NONE;
+ } else if (GEN_GEN == 8) {
+ /* Broadwell can sample from fast-cleared images */
+ att_state->input_aux_usage = ISL_AUX_USAGE_CCS_D;
+ } else {
+ /* Ivy Bridge and Haswell cannot */
+ att_state->input_aux_usage = ISL_AUX_USAGE_NONE;
+ }
} else {
att_state->aux_usage = ISL_AUX_USAGE_NONE;
att_state->input_aux_usage = ISL_AUX_USAGE_NONE;
if (!(att->usage & VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT))
return false;
- /* We only allocate input attachment states for color and depth surfaces.
- * Stencil doesn't allow compression so we can just use the texture surface
- * state from the view
+ /* We only allocate input attachment states for color surfaces. Compression
+ * is not yet enabled for depth textures and stencil doesn't allow
+ * compression so we can just use the texture surface state from the view.
+ */
+ return vk_format_is_color(att->format);
+}
+
+static enum isl_aux_usage
+layout_to_hiz_usage(VkImageLayout layout, uint8_t samples)
+{
+ switch (layout) {
+ case VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL:
+ return ISL_AUX_USAGE_HIZ;
+ case VK_IMAGE_LAYOUT_DEPTH_STENCIL_READ_ONLY_OPTIMAL:
+ case VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL:
+ if (anv_can_sample_with_hiz(GEN_GEN, samples))
+ return ISL_AUX_USAGE_HIZ;
+ /* Fall-through */
+ case VK_IMAGE_LAYOUT_GENERAL:
+ /* This buffer could be used as a source or destination in a transfer
+ * operation. Transfer operations current don't perform HiZ-enabled reads
+ * and writes.
+ */
+ default:
+ return ISL_AUX_USAGE_NONE;
+ }
+}
+
+/* Transitions a HiZ-enabled depth buffer from one layout to another. Unless
+ * the initial layout is undefined, the HiZ buffer and depth buffer will
+ * represent the same data at the end of this operation.
+ */
+static void
+transition_depth_buffer(struct anv_cmd_buffer *cmd_buffer,
+ const struct anv_image *image,
+ VkImageLayout initial_layout,
+ VkImageLayout final_layout)
+{
+ assert(image);
+
+ if (image->aux_usage != ISL_AUX_USAGE_HIZ || final_layout == initial_layout)
+ return;
+
+ const bool hiz_enabled = layout_to_hiz_usage(initial_layout, image->samples) ==
+ ISL_AUX_USAGE_HIZ;
+ const bool enable_hiz = layout_to_hiz_usage(final_layout, image->samples) ==
+ ISL_AUX_USAGE_HIZ;
+
+ enum blorp_hiz_op hiz_op;
+ if (initial_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
+ /* We've already initialized the aux HiZ buffer at BindImageMemory time,
+ * so there's no need to perform a HIZ resolve or clear to avoid GPU hangs.
+ * This initial layout indicates that the user doesn't care about the data
+ * that's currently in the buffer, so resolves are not necessary except
+ * for the special case noted below.
+ */
+ hiz_op = BLORP_HIZ_OP_NONE;
+ } else if (hiz_enabled && !enable_hiz) {
+ hiz_op = BLORP_HIZ_OP_DEPTH_RESOLVE;
+ } else if (!hiz_enabled && enable_hiz) {
+ hiz_op = BLORP_HIZ_OP_HIZ_RESOLVE;
+ } else {
+ assert(hiz_enabled == enable_hiz);
+ /* If the same buffer will be used, no resolves are necessary except for
+ * the special case noted below.
+ */
+ hiz_op = BLORP_HIZ_OP_NONE;
+ }
+
+ if (hiz_op != BLORP_HIZ_OP_NONE)
+ anv_gen8_hiz_op_resolve(cmd_buffer, image, hiz_op);
+
+ /* Images that have sampling with HiZ enabled cause all shader sampling to
+ * load data with the HiZ buffer. Therefore, in the case of transitioning to
+ * the general layout - which currently routes all writes to the depth
+ * buffer - we must ensure that the HiZ buffer remains consistent with the
+ * depth buffer by performing an additional HIZ resolve if the operation
+ * required by this transition was not already a HiZ resolve.
*/
- return vk_format_is_color(att->format) || vk_format_has_depth(att->format);
+ if (final_layout == VK_IMAGE_LAYOUT_GENERAL &&
+ anv_can_sample_with_hiz(GEN_GEN, image->samples) &&
+ hiz_op != BLORP_HIZ_OP_HIZ_RESOLVE) {
+ anv_gen8_hiz_op_resolve(cmd_buffer, image, BLORP_HIZ_OP_HIZ_RESOLVE);
+ }
}
+
/**
* Setup anv_cmd_state::attachments for vkCmdBeginRenderPass.
*/
}
}
+ state->attachments[i].current_layout = att->initial_layout;
state->attachments[i].pending_clear_aspects = clear_aspects;
if (clear_aspects)
state->attachments[i].clear_value = begin->pClearValues[i];
struct isl_view view = iview->isl;
view.usage |= ISL_SURF_USAGE_RENDER_TARGET_BIT;
+ view.swizzle = anv_swizzle_for_render(view.swizzle);
isl_surf_fill_state(isl_dev,
state->attachments[i].color_rt_state.map,
.surf = &iview->image->color_surface.isl,
state->attachments[i].aux_usage,
state->attachments[i].color_rt_state);
} else {
- state->attachments[i].aux_usage = ISL_AUX_USAGE_NONE;
+ if (iview->image->aux_usage == ISL_AUX_USAGE_HIZ) {
+ state->attachments[i].aux_usage =
+ layout_to_hiz_usage(att->initial_layout, iview->image->samples);
+ } else {
+ state->attachments[i].aux_usage = ISL_AUX_USAGE_NONE;
+ }
state->attachments[i].input_aux_usage = ISL_AUX_USAGE_NONE;
}
if (need_input_attachment_state(&pass->attachments[i])) {
- const struct isl_surf *surf;
- if (att_aspects == VK_IMAGE_ASPECT_COLOR_BIT) {
- surf = &iview->image->color_surface.isl;
- } else {
- surf = &iview->image->depth_surface.isl;
- }
-
struct isl_view view = iview->isl;
view.usage |= ISL_SURF_USAGE_TEXTURE_BIT;
isl_surf_fill_state(isl_dev,
state->attachments[i].input_att_state.map,
- .surf = surf,
+ .surf = &iview->image->color_surface.isl,
.view = &view,
.aux_surf = &iview->image->aux_surface.isl,
.aux_usage = state->attachments[i].input_aux_usage,
assert(!urb_low_bw || cfg->n[GEN_L3P_URB] == cfg->n[GEN_L3P_SLM]);
/* Minimum number of ways that can be allocated to the URB. */
- const unsigned n0_urb = (devinfo->is_baytrail ? 32 : 0);
+ MAYBE_UNUSED const unsigned n0_urb = devinfo->is_baytrail ? 32 : 0;
assert(cfg->n[GEN_L3P_URB] >= n0_urb);
uint32_t l3sqcr1, l3cr2, l3cr3;
for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
src_flags |= pImageMemoryBarriers[i].srcAccessMask;
dst_flags |= pImageMemoryBarriers[i].dstAccessMask;
+ ANV_FROM_HANDLE(anv_image, image, pImageMemoryBarriers[i].image);
+ if (pImageMemoryBarriers[i].subresourceRange.aspectMask &
+ VK_IMAGE_ASPECT_DEPTH_BIT) {
+ transition_depth_buffer(cmd_buffer, image,
+ pImageMemoryBarriers[i].oldLayout,
+ pImageMemoryBarriers[i].newLayout);
+ }
}
enum anv_pipe_bits pipe_bits = 0;
case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT:
assert(stage == MESA_SHADER_FRAGMENT);
- if (desc->image_view->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT) {
- /* For stencil input attachments, we treat it like any old texture
- * that a user may have bound.
+ if (desc->image_view->aspect_mask != VK_IMAGE_ASPECT_COLOR_BIT) {
+ /* For depth and stencil input attachments, we treat it like any
+ * old texture that a user may have bound.
*/
surface_state = desc->image_view->sampler_surface_state;
assert(surface_state.alloc_size);
desc->image_view->image->aux_usage,
surface_state);
} else {
- /* For depth and color input attachments, we create the surface
- * state at vkBeginRenderPass time so that we can include aux
- * and clear color information.
+ /* For color input attachments, we create the surface state at
+ * vkBeginRenderPass time so that we can include aux and clear
+ * color information.
*/
assert(binding->input_attachment_index < subpass->input_count);
const unsigned subpass_att = binding->input_attachment_index;
}
static void
-emit_base_vertex_instance_bo(struct anv_cmd_buffer *cmd_buffer,
- struct anv_bo *bo, uint32_t offset)
+emit_vertex_bo(struct anv_cmd_buffer *cmd_buffer,
+ struct anv_bo *bo, uint32_t offset,
+ uint32_t size, uint32_t index)
{
uint32_t *p = anv_batch_emitn(&cmd_buffer->batch, 5,
GENX(3DSTATE_VERTEX_BUFFERS));
GENX(VERTEX_BUFFER_STATE_pack)(&cmd_buffer->batch, p + 1,
&(struct GENX(VERTEX_BUFFER_STATE)) {
- .VertexBufferIndex = 32, /* Reserved for this */
+ .VertexBufferIndex = index,
.AddressModifyEnable = true,
.BufferPitch = 0,
#if (GEN_GEN >= 8)
.MemoryObjectControlState = GENX(MOCS),
.BufferStartingAddress = { bo, offset },
- .BufferSize = 8
+ .BufferSize = size
#else
.VertexBufferMemoryObjectControlState = GENX(MOCS),
.BufferStartingAddress = { bo, offset },
- .EndAddress = { bo, offset + 8 },
+ .EndAddress = { bo, offset + size },
#endif
});
}
+static void
+emit_base_vertex_instance_bo(struct anv_cmd_buffer *cmd_buffer,
+ struct anv_bo *bo, uint32_t offset)
+{
+ emit_vertex_bo(cmd_buffer, bo, offset, 8, ANV_SVGS_VB_INDEX);
+}
+
static void
emit_base_vertex_instance(struct anv_cmd_buffer *cmd_buffer,
uint32_t base_vertex, uint32_t base_instance)
&cmd_buffer->device->dynamic_state_block_pool.bo, id_state.offset);
}
+static void
+emit_draw_index(struct anv_cmd_buffer *cmd_buffer, uint32_t draw_index)
+{
+ struct anv_state state =
+ anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, 4, 4);
+
+ ((uint32_t *)state.map)[0] = draw_index;
+
+ if (!cmd_buffer->device->info.has_llc)
+ anv_state_clflush(state);
+
+ emit_vertex_bo(cmd_buffer,
+ &cmd_buffer->device->dynamic_state_block_pool.bo,
+ state.offset, 4, ANV_DRAWID_VB_INDEX);
+}
+
void genX(CmdDraw)(
VkCommandBuffer commandBuffer,
uint32_t vertexCount,
if (vs_prog_data->uses_basevertex || vs_prog_data->uses_baseinstance)
emit_base_vertex_instance(cmd_buffer, firstVertex, firstInstance);
+ if (vs_prog_data->uses_drawid)
+ emit_draw_index(cmd_buffer, 0);
anv_batch_emit(&cmd_buffer->batch, GENX(3DPRIMITIVE), prim) {
prim.VertexAccessType = SEQUENTIAL;
if (vs_prog_data->uses_basevertex || vs_prog_data->uses_baseinstance)
emit_base_vertex_instance(cmd_buffer, vertexOffset, firstInstance);
+ if (vs_prog_data->uses_drawid)
+ emit_draw_index(cmd_buffer, 0);
anv_batch_emit(&cmd_buffer->batch, GENX(3DPRIMITIVE), prim) {
prim.VertexAccessType = RANDOM;
if (vs_prog_data->uses_basevertex || vs_prog_data->uses_baseinstance)
emit_base_vertex_instance_bo(cmd_buffer, bo, bo_offset + 8);
+ if (vs_prog_data->uses_drawid)
+ emit_draw_index(cmd_buffer, 0);
emit_lrm(&cmd_buffer->batch, GEN7_3DPRIM_VERTEX_COUNT, bo, bo_offset);
emit_lrm(&cmd_buffer->batch, GEN7_3DPRIM_INSTANCE_COUNT, bo, bo_offset + 4);
/* TODO: We need to stomp base vertex to 0 somehow */
if (vs_prog_data->uses_basevertex || vs_prog_data->uses_baseinstance)
emit_base_vertex_instance_bo(cmd_buffer, bo, bo_offset + 12);
+ if (vs_prog_data->uses_drawid)
+ emit_draw_index(cmd_buffer, 0);
emit_lrm(&cmd_buffer->batch, GEN7_3DPRIM_VERTEX_COUNT, bo, bo_offset);
emit_lrm(&cmd_buffer->batch, GEN7_3DPRIM_INSTANCE_COUNT, bo, bo_offset + 4);
}
}
+static uint32_t
+depth_stencil_surface_type(enum isl_surf_dim dim)
+{
+ switch (dim) {
+ case ISL_SURF_DIM_1D:
+ if (GEN_GEN >= 9) {
+ /* From the Sky Lake PRM, 3DSTATAE_DEPTH_BUFFER::SurfaceType
+ *
+ * Programming Notes:
+ * The Surface Type of the depth buffer must be the same as the
+ * Surface Type of the render target(s) (defined in
+ * SURFACE_STATE), unless either the depth buffer or render
+ * targets are SURFTYPE_NULL (see exception below for SKL). 1D
+ * surface type not allowed for depth surface and stencil surface.
+ *
+ * Workaround:
+ * If depth/stencil is enabled with 1D render target,
+ * depth/stencil surface type needs to be set to 2D surface type
+ * and height set to 1. Depth will use (legacy) TileY and stencil
+ * will use TileW. For this case only, the Surface Type of the
+ * depth buffer can be 2D while the Surface Type of the render
+ * target(s) are 1D, representing an exception to a programming
+ * note above.
+ */
+ return SURFTYPE_2D;
+ } else {
+ return SURFTYPE_1D;
+ }
+ case ISL_SURF_DIM_2D:
+ return SURFTYPE_2D;
+ case ISL_SURF_DIM_3D:
+ if (GEN_GEN >= 9) {
+ /* The Sky Lake docs list the value for 3D as "Reserved". However,
+ * they have the exact same layout as 2D arrays on gen9+, so we can
+ * just use 2D here.
+ */
+ return SURFTYPE_2D;
+ } else {
+ return SURFTYPE_3D;
+ }
+ default:
+ unreachable("Invalid surface dimension");
+ }
+}
+
static void
cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer *cmd_buffer)
{
anv_cmd_buffer_get_depth_stencil_view(cmd_buffer);
const struct anv_image *image = iview ? iview->image : NULL;
const bool has_depth = image && (image->aspects & VK_IMAGE_ASPECT_DEPTH_BIT);
- const bool has_hiz = image != NULL && anv_image_has_hiz(image);
+ const uint32_t ds = cmd_buffer->state.subpass->depth_stencil_attachment;
+ const bool has_hiz = image != NULL &&
+ cmd_buffer->state.attachments[ds].aux_usage == ISL_AUX_USAGE_HIZ;
const bool has_stencil =
image && (image->aspects & VK_IMAGE_ASPECT_STENCIL_BIT);
/* Emit 3DSTATE_DEPTH_BUFFER */
if (has_depth) {
anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_DEPTH_BUFFER), db) {
- db.SurfaceType = SURFTYPE_2D;
+ db.SurfaceType =
+ depth_stencil_surface_type(image->depth_surface.isl.dim);
db.DepthWriteEnable = true;
db.StencilWriteEnable = has_stencil;
-
- if (cmd_buffer->state.pass->subpass_count == 1) {
- db.HierarchicalDepthBufferEnable = has_hiz;
- } else {
- anv_finishme("Multiple-subpass HiZ not implemented");
- }
+ db.HierarchicalDepthBufferEnable = has_hiz;
db.SurfaceFormat = isl_surf_get_depth_format(&device->isl_dev,
&image->depth_surface.isl);
db.Height = image->extent.height - 1;
db.Width = image->extent.width - 1;
db.LOD = iview->isl.base_level;
- db.Depth = image->array_size - 1; /* FIXME: 3-D */
db.MinimumArrayElement = iview->isl.base_array_layer;
+ assert(image->depth_surface.isl.dim != ISL_SURF_DIM_3D);
+ db.Depth =
+ db.RenderTargetViewExtent =
+ iview->isl.array_len - iview->isl.base_array_layer - 1;
+
#if GEN_GEN >= 8
db.SurfaceQPitch =
isl_surf_get_array_pitch_el_rows(&image->depth_surface.isl) >> 2;
#endif
- db.RenderTargetViewExtent = 1 - 1;
}
} else {
/* Even when no depth buffer is present, the hardware requires that
* be combined with a stencil buffer so we use D32_FLOAT instead.
*/
anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_DEPTH_BUFFER), db) {
- db.SurfaceType = SURFTYPE_2D;
+ if (has_stencil) {
+ db.SurfaceType =
+ depth_stencil_surface_type(image->stencil_surface.isl.dim);
+ } else {
+ db.SurfaceType = SURFTYPE_2D;
+ }
db.SurfaceFormat = D32_FLOAT;
- db.Width = fb->width - 1;
- db.Height = fb->height - 1;
+ db.Width = MAX2(fb->width, 1) - 1;
+ db.Height = MAX2(fb->height, 1) - 1;
db.StencilWriteEnable = has_stencil;
}
}
* - SURFTYPE_1D: distance in pixels between array slices
* - SURFTYPE_2D/CUBE: distance in rows between array slices
* - SURFTYPE_3D: distance in rows between R - slices
+ *
+ * Unfortunately, the docs aren't 100% accurate here. They fail to
+ * mention that the 1-D rule only applies to linear 1-D images.
+ * Since depth and HiZ buffers are always tiled, they are treated as
+ * 2-D images. Prior to Sky Lake, this field is always in rows.
*/
hdb.SurfaceQPitch =
- image->aux_surface.isl.dim == ISL_SURF_DIM_1D ?
- isl_surf_get_array_pitch_el(&image->aux_surface.isl) >> 2 :
- isl_surf_get_array_pitch_el_rows(&image->aux_surface.isl) >> 2;
+ isl_surf_get_array_pitch_sa_rows(&image->aux_surface.isl) >> 2;
#endif
}
} else {
anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CLEAR_PARAMS), cp) {
if (has_hiz) {
cp.DepthClearValueValid = true;
- const uint32_t ds =
- cmd_buffer->state.subpass->depth_stencil_attachment;
- cp.DepthClearValue =
- cmd_buffer->state.attachments[ds].clear_value.depthStencil.depth;
+ cp.DepthClearValue = ANV_HZ_FC_VAL;
}
}
}
cmd_buffer->state.dirty |= ANV_CMD_DIRTY_RENDER_TARGETS;
+ const struct anv_image_view *iview =
+ anv_cmd_buffer_get_depth_stencil_view(cmd_buffer);
+
+ if (iview && iview->image->aux_usage == ISL_AUX_USAGE_HIZ) {
+ const uint32_t ds = subpass->depth_stencil_attachment;
+ transition_depth_buffer(cmd_buffer, iview->image,
+ cmd_buffer->state.attachments[ds].current_layout,
+ cmd_buffer->state.subpass->depth_stencil_layout);
+ cmd_buffer->state.attachments[ds].current_layout =
+ cmd_buffer->state.subpass->depth_stencil_layout;
+ cmd_buffer->state.attachments[ds].aux_usage =
+ layout_to_hiz_usage(cmd_buffer->state.subpass->depth_stencil_layout,
+ iview->image->samples);
+ }
+
cmd_buffer_emit_depth_stencil(cmd_buffer);
- genX(cmd_buffer_emit_hz_op)(cmd_buffer, BLORP_HIZ_OP_HIZ_RESOLVE);
- genX(cmd_buffer_emit_hz_op)(cmd_buffer, BLORP_HIZ_OP_DEPTH_CLEAR);
anv_cmd_buffer_clear_subpass(cmd_buffer);
}
assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
+ const struct anv_image_view *iview =
+ anv_cmd_buffer_get_depth_stencil_view(cmd_buffer);
+
+ if (iview && iview->image->aux_usage == ISL_AUX_USAGE_HIZ) {
+ const uint32_t ds = cmd_buffer->state.subpass->depth_stencil_attachment;
+
+ if (cmd_buffer->state.subpass - cmd_buffer->state.pass->subpasses ==
+ cmd_buffer->state.pass->attachments[ds].last_subpass_idx) {
+ transition_depth_buffer(cmd_buffer, iview->image,
+ cmd_buffer->state.attachments[ds].current_layout,
+ cmd_buffer->state.pass->attachments[ds].final_layout);
+ }
+ }
+
anv_cmd_buffer_resolve_subpass(cmd_buffer);
genX(cmd_buffer_set_subpass)(cmd_buffer, cmd_buffer->state.subpass + 1);
}
{
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
- genX(cmd_buffer_emit_hz_op)(cmd_buffer, BLORP_HIZ_OP_DEPTH_RESOLVE);
+ const struct anv_image_view *iview =
+ anv_cmd_buffer_get_depth_stencil_view(cmd_buffer);
+
+ if (iview && iview->image->aux_usage == ISL_AUX_USAGE_HIZ) {
+ const uint32_t ds = cmd_buffer->state.subpass->depth_stencil_attachment;
+
+ if (cmd_buffer->state.subpass - cmd_buffer->state.pass->subpasses ==
+ cmd_buffer->state.pass->attachments[ds].last_subpass_idx) {
+ transition_depth_buffer(cmd_buffer, iview->image,
+ cmd_buffer->state.attachments[ds].current_layout,
+ cmd_buffer->state.pass->attachments[ds].final_layout);
+ }
+ }
+
anv_cmd_buffer_resolve_subpass(cmd_buffer);
#ifndef NDEBUG
projects / mesa.git / blobdiff