{
*stencilWriteEnable = state->stencilTestEnable;
- /* If the depth test is disabled, we won't be writing anything. */
- if (!state->depthTestEnable)
- state->depthWriteEnable = false;
-
- /* The Vulkan spec requires that if either depth or stencil is not present,
- * the pipeline is to act as if the test silently passes.
+ /* If the depth test is disabled, we won't be writing anything. Make sure we
+ * treat the test as always passing later on as well.
+ *
+ * Also, the Vulkan spec requires that if either depth or stencil is not
+ * present, the pipeline is to act as if the test silently passes. In that
+ * case we won't write either.
*/
- if (!(ds_aspects & VK_IMAGE_ASPECT_DEPTH_BIT)) {
+ if (!state->depthTestEnable || !(ds_aspects & VK_IMAGE_ASPECT_DEPTH_BIT)) {
state->depthWriteEnable = false;
state->depthCompareOp = VK_COMPARE_OP_ALWAYS;
}
#endif
}
+MAYBE_UNUSED static bool
+is_dual_src_blend_factor(VkBlendFactor factor)
+{
+ return factor == VK_BLEND_FACTOR_SRC1_COLOR ||
+ factor == VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR ||
+ factor == VK_BLEND_FACTOR_SRC1_ALPHA ||
+ factor == VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA;
+}
+
static void
emit_cb_state(struct anv_pipeline *pipeline,
const VkPipelineColorBlendStateCreateInfo *info,
const VkPipelineMultisampleStateCreateInfo *ms_info)
{
struct anv_device *device = pipeline->device;
-
+ const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
struct GENX(BLEND_STATE) blend_state = {
#if GEN_GEN >= 8
#endif
}
+ /* The Dual Source Blending documentation says:
+ *
+ * "If SRC1 is included in a src/dst blend factor and
+ * a DualSource RT Write message is not used, results
+ * are UNDEFINED. (This reflects the same restriction in DX APIs,
+ * where undefined results are produced if “o1” is not written
+ * by a PS – there are no default values defined)."
+ *
+ * There is no way to gracefully fix this undefined situation
+ * so we just disable the blending to prevent possible issues.
+ */
+ if (!wm_prog_data->dual_src_blend &&
+ (is_dual_src_blend_factor(a->srcColorBlendFactor) ||
+ is_dual_src_blend_factor(a->dstColorBlendFactor) ||
+ is_dual_src_blend_factor(a->srcAlphaBlendFactor) ||
+ is_dual_src_blend_factor(a->dstAlphaBlendFactor))) {
+ vk_debug_report(&device->instance->debug_report_callbacks,
+ VK_DEBUG_REPORT_WARNING_BIT_EXT,
+ VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT,
+ (uint64_t)(uintptr_t)device,
+ 0, 0, "anv",
+ "Enabled dual-src blend factors without writing both targets "
+ "in the shader. Disabling blending to avoid GPU hangs.");
+ entry.ColorBufferBlendEnable = false;
+ }
+
if (a->colorWriteMask != 0)
has_writeable_rt = true;
clip.FrontWinding = vk_to_gen_front_face[rs_info->frontFace];
clip.CullMode = vk_to_gen_cullmode[rs_info->cullMode];
clip.ViewportZClipTestEnable = !pipeline->depth_clamp_enable;
- if (last) {
- clip.UserClipDistanceClipTestEnableBitmask = last->clip_distance_mask;
- clip.UserClipDistanceCullTestEnableBitmask = last->cull_distance_mask;
- }
+ clip.UserClipDistanceClipTestEnableBitmask = last->clip_distance_mask;
+ clip.UserClipDistanceCullTestEnableBitmask = last->cull_distance_mask;
#else
clip.NonPerspectiveBarycentricEnable = wm_prog_data ?
(wm_prog_data->barycentric_interp_modes &
vs.SingleVertexDispatch = false;
#endif
vs.VectorMaskEnable = false;
- vs.SamplerCount = get_sampler_count(vs_bin);
+ /* WA_1606682166:
+ * Incorrect TDL's SSP address shift in SARB for 16:6 & 18:8 modes.
+ * Disable the Sampler state prefetch functionality in the SARB by
+ * programming 0xB000[30] to '1'.
+ */
+ vs.SamplerCount = GEN_GEN == 11 ? 0 : get_sampler_count(vs_bin);
/* Gen 11 workarounds table #2056 WABTPPrefetchDisable suggests to
* disable prefetching of binding tables on A0 and B0 steppings.
* TODO: Revisit this WA on newer steppings.
hs.Enable = true;
hs.StatisticsEnable = true;
hs.KernelStartPointer = tcs_bin->kernel.offset;
-
- hs.SamplerCount = get_sampler_count(tcs_bin);
+ /* WA_1606682166 */
+ hs.SamplerCount = GEN_GEN == 11 ? 0 : get_sampler_count(tcs_bin);
/* Gen 11 workarounds table #2056 WABTPPrefetchDisable */
hs.BindingTableEntryCount = GEN_GEN == 11 ? 0 : get_binding_table_entry_count(tcs_bin);
hs.MaximumNumberofThreads = devinfo->max_tcs_threads - 1;
get_scratch_address(pipeline, MESA_SHADER_TESS_CTRL, tcs_bin);
}
- const VkPipelineTessellationDomainOriginStateCreateInfoKHR *domain_origin_state =
- tess_info ? vk_find_struct_const(tess_info, PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO_KHR) : NULL;
+ const VkPipelineTessellationDomainOriginStateCreateInfo *domain_origin_state =
+ tess_info ? vk_find_struct_const(tess_info, PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO) : NULL;
- VkTessellationDomainOriginKHR uv_origin =
+ VkTessellationDomainOrigin uv_origin =
domain_origin_state ? domain_origin_state->domainOrigin :
- VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT_KHR;
+ VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT;
anv_batch_emit(&pipeline->batch, GENX(3DSTATE_TE), te) {
te.Partitioning = tes_prog_data->partitioning;
- if (uv_origin == VK_TESSELLATION_DOMAIN_ORIGIN_LOWER_LEFT_KHR) {
+ if (uv_origin == VK_TESSELLATION_DOMAIN_ORIGIN_LOWER_LEFT) {
te.OutputTopology = tes_prog_data->output_topology;
} else {
/* When the origin is upper-left, we have to flip the winding order */
ds.Enable = true;
ds.StatisticsEnable = true;
ds.KernelStartPointer = tes_bin->kernel.offset;
-
- ds.SamplerCount = get_sampler_count(tes_bin);
+ /* WA_1606682166 */
+ ds.SamplerCount = GEN_GEN == 11 ? 0 : get_sampler_count(tes_bin);
/* Gen 11 workarounds table #2056 WABTPPrefetchDisable */
ds.BindingTableEntryCount = GEN_GEN == 11 ? 0 : get_binding_table_entry_count(tes_bin);
ds.MaximumNumberofThreads = devinfo->max_tes_threads - 1;
gs.SingleProgramFlow = false;
gs.VectorMaskEnable = false;
- gs.SamplerCount = get_sampler_count(gs_bin);
+ /* WA_1606682166 */
+ gs.SamplerCount = GEN_GEN == 11 ? 0 : get_sampler_count(gs_bin);
/* Gen 11 workarounds table #2056 WABTPPrefetchDisable */
gs.BindingTableEntryCount = GEN_GEN == 11 ? 0 : get_binding_table_entry_count(gs_bin);
gs.IncludeVertexHandles = gs_prog_data->base.include_vue_handles;
wm.EarlyDepthStencilControl = EDSC_NORMAL;
}
-#if GEN_GEN == 8
- /* Gen8 and later hardware tries to compute ThreadDispatchEnable for
- * us but doesn't take into account KillPixels when no depth or
- * stencil writes are enabled. In order for occlusion queries to
- * work correctly with no attachments, we need to force-enable PS
- * thread dispatch.
+#if GEN_GEN >= 8
+ /* Gen8 hardware tries to compute ThreadDispatchEnable for us but
+ * doesn't take into account KillPixels when no depth or stencil
+ * writes are enabled. In order for occlusion queries to work
+ * correctly with no attachments, we need to force-enable PS thread
+ * dispatch.
*
* The BDW docs are pretty clear that that this bit isn't validated
* and probably shouldn't be used in production:
*
* Unfortunately, however, the other mechanism we have for doing this
* is 3DSTATE_PS_EXTRA::PixelShaderHasUAV which causes hangs on BDW.
- * Given two bad options, we choose the one which works. On Skylake
- * and later, setting ForceThreadDispatchEnable causes GPU hangs so
- * we use the PixelShaderHasUAV mechanism there.
+ * Given two bad options, we choose the one which works.
*/
if ((wm_prog_data->has_side_effects || wm_prog_data->uses_kill) &&
!has_color_buffer_write_enabled(pipeline, blend))
}
}
-UNUSED static bool
-is_dual_src_blend_factor(VkBlendFactor factor)
-{
- return factor == VK_BLEND_FACTOR_SRC1_COLOR ||
- factor == VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR ||
- factor == VK_BLEND_FACTOR_SRC1_ALPHA ||
- factor == VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA;
-}
-
static void
emit_3dstate_ps(struct anv_pipeline *pipeline,
const VkPipelineColorBlendStateCreateInfo *blend,
ps.SingleProgramFlow = false;
ps.VectorMaskEnable = true;
- ps.SamplerCount = get_sampler_count(fs_bin);
+ /* WA_1606682166 */
+ ps.SamplerCount = GEN_GEN == 11 ? 0 : get_sampler_count(fs_bin);
/* Gen 11 workarounds table #2056 WABTPPrefetchDisable */
ps.BindingTableEntryCount = GEN_GEN == 11 ? 0 : get_binding_table_entry_count(fs_bin);
ps.PushConstantEnable = wm_prog_data->base.nr_params > 0 ||
wm_prog_data->uses_kill;
#if GEN_GEN >= 9
- /* Gen8 and later hardware tries to compute ThreadDispatchEnable for us
- * but doesn't take into account KillPixels when no depth or stencil
- * writes are enabled. In order for occlusion queries to work correctly
- * with no attachments, we need to force-enable PS thread dispatch.
- *
- * The stricter cross-primitive coherency guarantees that the hardware
- * gives us with the "Accesses UAV" bit set for at least one shader stage
- * and the "UAV coherency required" bit set on the 3DPRIMITIVE command are
- * redundant within the current image, atomic counter and SSBO GL and
- * Vulkan APIs, which all have very loose ordering and coherency
- * requirements and generally rely on the application to insert explicit
- * barriers when a shader invocation is expected to see the memory
- * writes performed by the invocations of some previous primitive.
- * Regardless of the value of "UAV coherency required", the "Accesses
- * UAV" bits will implicitly cause an in most cases useless DC flush
- * when the lowermost stage with the bit set finishes execution.
- *
- * Unfortunately, however, the other mechanism we have for doing this is
- * 3DSTATE_WM::ForceThreadDispatchEnable which causes GPU hangs on
- * Skylake and later hardware. On Broadwell, however, setting this bit
- * causes GPU hangs so we use ForceThreadDispatchEnable there.
- */
- if ((wm_prog_data->has_side_effects || wm_prog_data->uses_kill) &&
- !has_color_buffer_write_enabled(pipeline, blend))
- ps.PixelShaderHasUAV = true;
-
ps.PixelShaderComputesStencil = wm_prog_data->computed_stencil;
ps.PixelShaderPullsBary = wm_prog_data->pulls_bary;
struct GENX(INTERFACE_DESCRIPTOR_DATA) desc = {
.KernelStartPointer = cs_bin->kernel.offset,
-
- .SamplerCount = get_sampler_count(cs_bin),
- /* Gen 11 workarounds table #2056 WABTPPrefetchDisable */
- .BindingTableEntryCount = GEN_GEN == 11 ? 0 : get_binding_table_entry_count(cs_bin),
+ /* WA_1606682166 */
+ .SamplerCount = GEN_GEN == 11 ? 0 : get_sampler_count(cs_bin),
+ /* Gen 11 workarounds table #2056 WABTPPrefetchDisable
+ *
+ * We add 1 because the CS indirect parameters buffer isn't accounted
+ * for in bind_map.surface_count.
+ */
+ .BindingTableEntryCount = GEN_GEN == 11 ? 0 : 1 + MIN2(cs_bin->bind_map.surface_count, 30),
.BarrierEnable = cs_prog_data->uses_barrier,
.SharedLocalMemorySize =
encode_slm_size(GEN_GEN, cs_prog_data->base.total_shared),
projects / mesa.git / blobdiff