VkQueryPool* pQueryPool)
{
ANV_FROM_HANDLE(anv_device, device, _device);
+ const struct anv_physical_device *pdevice = &device->instance->physicalDevice;
struct anv_query_pool *pool;
VkResult result;
pipeline_statistics &= ANV_PIPELINE_STATISTICS_MASK;
/* Statistics queries have a min and max for every statistic */
- uint64s_per_slot += 2 * _mesa_bitcount(pipeline_statistics);
+ uint64s_per_slot += 2 * util_bitcount(pipeline_statistics);
break;
default:
assert(!"Invalid query type");
if (result != VK_SUCCESS)
goto fail;
+ if (pdevice->supports_48bit_addresses)
+ pool->bo.flags |= EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+
+ if (pdevice->use_softpin)
+ pool->bo.flags |= EXEC_OBJECT_PINNED;
+
+ if (pdevice->has_exec_async)
+ pool->bo.flags |= EXEC_OBJECT_ASYNC;
+
+ anv_vma_alloc(device, &pool->bo);
+
/* For query pools, we set the caching mode to I915_CACHING_CACHED. On LLC
* platforms, this does nothing. On non-LLC platforms, this means snooping
* which comes at a slight cost. However, the buffers aren't big, won't be
return;
anv_gem_munmap(pool->bo.map, pool->bo.size);
+ anv_vma_free(device, &pool->bo);
anv_gem_close(device, pool->bo.gem_handle);
vk_free2(&device->alloc, pAllocator, pool);
}
+static struct anv_address
+anv_query_address(struct anv_query_pool *pool, uint32_t query)
+{
+ return (struct anv_address) {
+ .bo = &pool->bo,
+ .offset = query * pool->stride,
+ };
+}
+
static void
cpu_write_query_result(void *dst_slot, VkQueryResultFlags flags,
uint32_t value_index, uint64_t result)
} else if (ret == -1) {
/* We don't know the real error. */
device->lost = true;
- return vk_errorf(VK_ERROR_DEVICE_LOST, "gem wait failed: %m");
+ return vk_errorf(device->instance, device, VK_ERROR_DEVICE_LOST,
+ "gem wait failed: %m");
} else {
assert(ret == 0);
/* The BO is no longer busy. */
*/
bool write_results = available || (flags & VK_QUERY_RESULT_PARTIAL_BIT);
- if (write_results) {
- switch (pool->type) {
- case VK_QUERY_TYPE_OCCLUSION: {
- cpu_write_query_result(pData, flags, 0, slot[2] - slot[1]);
- break;
- }
+ uint32_t idx = 0;
+ switch (pool->type) {
+ case VK_QUERY_TYPE_OCCLUSION:
+ if (write_results)
+ cpu_write_query_result(pData, flags, idx, slot[2] - slot[1]);
+ idx++;
+ break;
- case VK_QUERY_TYPE_PIPELINE_STATISTICS: {
- uint32_t statistics = pool->pipeline_statistics;
- uint32_t idx = 0;
- while (statistics) {
- uint32_t stat = u_bit_scan(&statistics);
+ case VK_QUERY_TYPE_PIPELINE_STATISTICS: {
+ uint32_t statistics = pool->pipeline_statistics;
+ while (statistics) {
+ uint32_t stat = u_bit_scan(&statistics);
+ if (write_results) {
uint64_t result = slot[idx * 2 + 2] - slot[idx * 2 + 1];
/* WaDividePSInvocationCountBy4:HSW,BDW */
result >>= 2;
cpu_write_query_result(pData, flags, idx, result);
-
- idx++;
}
- assert(idx == _mesa_bitcount(pool->pipeline_statistics));
- break;
+ idx++;
}
+ assert(idx == util_bitcount(pool->pipeline_statistics));
+ break;
+ }
- case VK_QUERY_TYPE_TIMESTAMP: {
- cpu_write_query_result(pData, flags, 0, slot[1]);
- break;
- }
- default:
- unreachable("invalid pool type");
- }
- } else {
- status = VK_NOT_READY;
+ case VK_QUERY_TYPE_TIMESTAMP:
+ if (write_results)
+ cpu_write_query_result(pData, flags, idx, slot[1]);
+ idx++;
+ break;
+
+ default:
+ unreachable("invalid pool type");
}
- if (flags & VK_QUERY_RESULT_WITH_AVAILABILITY_BIT) {
- uint32_t idx = (pool->type == VK_QUERY_TYPE_PIPELINE_STATISTICS) ?
- _mesa_bitcount(pool->pipeline_statistics) : 1;
+ if (!write_results)
+ status = VK_NOT_READY;
+
+ if (flags & VK_QUERY_RESULT_WITH_AVAILABILITY_BIT)
cpu_write_query_result(pData, flags, idx, available);
- }
pData += stride;
if (pData >= data_end)
return status;
}
+static void
+emit_srm32(struct anv_batch *batch, struct anv_address addr, uint32_t reg)
+{
+ anv_batch_emit(batch, GENX(MI_STORE_REGISTER_MEM), srm) {
+ srm.MemoryAddress = addr;
+ srm.RegisterAddress = reg;
+ }
+}
+
+static void
+emit_srm64(struct anv_batch *batch, struct anv_address addr, uint32_t reg)
+{
+ emit_srm32(batch, anv_address_add(addr, 0), reg + 0);
+ emit_srm32(batch, anv_address_add(addr, 4), reg + 4);
+}
+
static void
emit_ps_depth_count(struct anv_cmd_buffer *cmd_buffer,
- struct anv_bo *bo, uint32_t offset)
+ struct anv_address addr)
{
anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
pc.DestinationAddressType = DAT_PPGTT;
pc.PostSyncOperation = WritePSDepthCount;
pc.DepthStallEnable = true;
- pc.Address = (struct anv_address) { bo, offset };
+ pc.Address = addr;
if (GEN_GEN == 9 && cmd_buffer->device->info.gt == 4)
pc.CommandStreamerStallEnable = true;
static void
emit_query_availability(struct anv_cmd_buffer *cmd_buffer,
- struct anv_bo *bo, uint32_t offset)
+ struct anv_address addr)
{
anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
pc.DestinationAddressType = DAT_PPGTT;
pc.PostSyncOperation = WriteImmediateData;
- pc.Address = (struct anv_address) { bo, offset };
+ pc.Address = addr;
pc.ImmediateData = 1;
}
}
+/**
+ * Goes through a series of consecutive query indices in the given pool
+ * setting all element values to 0 and emitting them as available.
+ */
+static void
+emit_zero_queries(struct anv_cmd_buffer *cmd_buffer,
+ struct anv_query_pool *pool,
+ uint32_t first_index, uint32_t num_queries)
+{
+ for (uint32_t i = 0; i < num_queries; i++) {
+ struct anv_address slot_addr =
+ anv_query_address(pool, first_index + i);
+ genX(cmd_buffer_mi_memset)(cmd_buffer, anv_address_add(slot_addr, 8),
+ 0, pool->stride - 8);
+ emit_query_availability(cmd_buffer, slot_addr);
+ }
+}
+
void genX(CmdResetQueryPool)(
VkCommandBuffer commandBuffer,
VkQueryPool queryPool,
for (uint32_t i = 0; i < queryCount; i++) {
anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_DATA_IMM), sdm) {
- sdm.Address = (struct anv_address) {
- .bo = &pool->bo,
- .offset = (firstQuery + i) * pool->stride,
- };
+ sdm.Address = anv_query_address(pool, firstQuery + i);
sdm.ImmediateData = 0;
}
}
static void
emit_pipeline_stat(struct anv_cmd_buffer *cmd_buffer, uint32_t stat,
- struct anv_bo *bo, uint32_t offset)
+ struct anv_address addr)
{
STATIC_ASSERT(ANV_PIPELINE_STATISTICS_MASK ==
(1 << ARRAY_SIZE(vk_pipeline_stat_to_reg)) - 1);
assert(stat < ARRAY_SIZE(vk_pipeline_stat_to_reg));
- uint32_t reg = vk_pipeline_stat_to_reg[stat];
-
- anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_REGISTER_MEM), lrm) {
- lrm.RegisterAddress = reg,
- lrm.MemoryAddress = (struct anv_address) { bo, offset };
- }
- anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_REGISTER_MEM), lrm) {
- lrm.RegisterAddress = reg + 4,
- lrm.MemoryAddress = (struct anv_address) { bo, offset + 4 };
- }
+ emit_srm64(&cmd_buffer->batch, addr, vk_pipeline_stat_to_reg[stat]);
}
void genX(CmdBeginQuery)(
{
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
ANV_FROM_HANDLE(anv_query_pool, pool, queryPool);
-
- /* Workaround: When meta uses the pipeline with the VS disabled, it seems
- * that the pipelining of the depth write breaks. What we see is that
- * samples from the render pass clear leaks into the first query
- * immediately after the clear. Doing a pipecontrol with a post-sync
- * operation and DepthStallEnable seems to work around the issue.
- */
- if (cmd_buffer->state.need_query_wa) {
- cmd_buffer->state.need_query_wa = false;
- anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
- pc.DepthCacheFlushEnable = true;
- pc.DepthStallEnable = true;
- }
- }
+ struct anv_address query_addr = anv_query_address(pool, query);
switch (pool->type) {
case VK_QUERY_TYPE_OCCLUSION:
- emit_ps_depth_count(cmd_buffer, &pool->bo, query * pool->stride + 8);
+ emit_ps_depth_count(cmd_buffer, anv_address_add(query_addr, 8));
break;
case VK_QUERY_TYPE_PIPELINE_STATISTICS: {
}
uint32_t statistics = pool->pipeline_statistics;
- uint32_t offset = query * pool->stride + 8;
+ uint32_t offset = 8;
while (statistics) {
uint32_t stat = u_bit_scan(&statistics);
- emit_pipeline_stat(cmd_buffer, stat, &pool->bo, offset);
+ emit_pipeline_stat(cmd_buffer, stat,
+ anv_address_add(query_addr, offset));
offset += 16;
}
break;
{
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
ANV_FROM_HANDLE(anv_query_pool, pool, queryPool);
+ struct anv_address query_addr = anv_query_address(pool, query);
switch (pool->type) {
case VK_QUERY_TYPE_OCCLUSION:
- emit_ps_depth_count(cmd_buffer, &pool->bo, query * pool->stride + 16);
- emit_query_availability(cmd_buffer, &pool->bo, query * pool->stride);
+ emit_ps_depth_count(cmd_buffer, anv_address_add(query_addr, 16));
+ emit_query_availability(cmd_buffer, query_addr);
break;
case VK_QUERY_TYPE_PIPELINE_STATISTICS: {
}
uint32_t statistics = pool->pipeline_statistics;
- uint32_t offset = query * pool->stride + 16;
+ uint32_t offset = 16;
while (statistics) {
uint32_t stat = u_bit_scan(&statistics);
- emit_pipeline_stat(cmd_buffer, stat, &pool->bo, offset);
+ emit_pipeline_stat(cmd_buffer, stat,
+ anv_address_add(query_addr, offset));
offset += 16;
}
- emit_query_availability(cmd_buffer, &pool->bo, query * pool->stride);
+ emit_query_availability(cmd_buffer, query_addr);
break;
}
default:
unreachable("");
}
+
+ /* When multiview is active the spec requires that N consecutive query
+ * indices are used, where N is the number of active views in the subpass.
+ * The spec allows that we only write the results to one of the queries
+ * but we still need to manage result availability for all the query indices.
+ * Since we only emit a single query for all active views in the
+ * first index, mark the other query indices as being already available
+ * with result 0.
+ */
+ if (cmd_buffer->state.subpass && cmd_buffer->state.subpass->view_mask) {
+ const uint32_t num_queries =
+ util_bitcount(cmd_buffer->state.subpass->view_mask);
+ if (num_queries > 1)
+ emit_zero_queries(cmd_buffer, pool, query + 1, num_queries - 1);
+ }
}
#define TIMESTAMP 0x2358
{
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
ANV_FROM_HANDLE(anv_query_pool, pool, queryPool);
- uint32_t offset = query * pool->stride;
+ struct anv_address query_addr = anv_query_address(pool, query);
assert(pool->type == VK_QUERY_TYPE_TIMESTAMP);
switch (pipelineStage) {
case VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT:
- anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_REGISTER_MEM), srm) {
- srm.RegisterAddress = TIMESTAMP;
- srm.MemoryAddress = (struct anv_address) { &pool->bo, offset + 8 };
- }
- anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_REGISTER_MEM), srm) {
- srm.RegisterAddress = TIMESTAMP + 4;
- srm.MemoryAddress = (struct anv_address) { &pool->bo, offset + 12 };
- }
+ emit_srm64(&cmd_buffer->batch, anv_address_add(query_addr, 8), TIMESTAMP);
break;
default:
anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
pc.DestinationAddressType = DAT_PPGTT;
pc.PostSyncOperation = WriteTimestamp;
- pc.Address = (struct anv_address) { &pool->bo, offset + 8 };
+ pc.Address = anv_address_add(query_addr, 8);
if (GEN_GEN == 9 && cmd_buffer->device->info.gt == 4)
pc.CommandStreamerStallEnable = true;
break;
}
- emit_query_availability(cmd_buffer, &pool->bo, offset);
+ emit_query_availability(cmd_buffer, query_addr);
+
+ /* When multiview is active the spec requires that N consecutive query
+ * indices are used, where N is the number of active views in the subpass.
+ * The spec allows that we only write the results to one of the queries
+ * but we still need to manage result availability for all the query indices.
+ * Since we only emit a single query for all active views in the
+ * first index, mark the other query indices as being already available
+ * with result 0.
+ */
+ if (cmd_buffer->state.subpass && cmd_buffer->state.subpass->view_mask) {
+ const uint32_t num_queries =
+ util_bitcount(cmd_buffer->state.subpass->view_mask);
+ if (num_queries > 1)
+ emit_zero_queries(cmd_buffer, pool, query + 1, num_queries - 1);
+ }
}
#if GEN_GEN > 7 || GEN_IS_HASWELL
-#define alu_opcode(v) __gen_uint((v), 20, 31)
-#define alu_operand1(v) __gen_uint((v), 10, 19)
-#define alu_operand2(v) __gen_uint((v), 0, 9)
-#define alu(opcode, operand1, operand2) \
- alu_opcode(opcode) | alu_operand1(operand1) | alu_operand2(operand2)
-
-#define OPCODE_NOOP 0x000
-#define OPCODE_LOAD 0x080
-#define OPCODE_LOADINV 0x480
-#define OPCODE_LOAD0 0x081
-#define OPCODE_LOAD1 0x481
-#define OPCODE_ADD 0x100
-#define OPCODE_SUB 0x101
-#define OPCODE_AND 0x102
-#define OPCODE_OR 0x103
-#define OPCODE_XOR 0x104
-#define OPCODE_STORE 0x180
-#define OPCODE_STOREINV 0x580
-
-#define OPERAND_R0 0x00
-#define OPERAND_R1 0x01
-#define OPERAND_R2 0x02
-#define OPERAND_R3 0x03
-#define OPERAND_R4 0x04
-#define OPERAND_SRCA 0x20
-#define OPERAND_SRCB 0x21
-#define OPERAND_ACCU 0x31
-#define OPERAND_ZF 0x32
-#define OPERAND_CF 0x33
+static uint32_t
+mi_alu(uint32_t opcode, uint32_t operand1, uint32_t operand2)
+{
+ struct GENX(MI_MATH_ALU_INSTRUCTION) instr = {
+ .ALUOpcode = opcode,
+ .Operand1 = operand1,
+ .Operand2 = operand2,
+ };
+
+ uint32_t dw;
+ GENX(MI_MATH_ALU_INSTRUCTION_pack)(NULL, &dw, &instr);
+
+ return dw;
+}
#define CS_GPR(n) (0x2600 + (n) * 8)
static void
emit_load_alu_reg_u64(struct anv_batch *batch, uint32_t reg,
- struct anv_bo *bo, uint32_t offset)
+ struct anv_address addr)
{
anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_MEM), lrm) {
- lrm.RegisterAddress = reg,
- lrm.MemoryAddress = (struct anv_address) { bo, offset };
+ lrm.RegisterAddress = reg;
+ lrm.MemoryAddress = anv_address_add(addr, 0);
}
anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_MEM), lrm) {
lrm.RegisterAddress = reg + 4;
- lrm.MemoryAddress = (struct anv_address) { bo, offset + 4 };
+ lrm.MemoryAddress = anv_address_add(addr, 4);
}
}
emit_load_alu_reg_imm64(batch, CS_GPR(1), (1ull << n) - 1);
uint32_t *dw = anv_batch_emitn(batch, 5, GENX(MI_MATH));
- dw[1] = alu(OPCODE_LOAD, OPERAND_SRCA, OPERAND_R0);
- dw[2] = alu(OPCODE_LOAD, OPERAND_SRCB, OPERAND_R1);
- dw[3] = alu(OPCODE_AND, 0, 0);
- dw[4] = alu(OPCODE_STORE, OPERAND_R0, OPERAND_ACCU);
+ if (!dw) {
+ anv_batch_set_error(batch, VK_ERROR_OUT_OF_HOST_MEMORY);
+ return;
+ }
+
+ dw[1] = mi_alu(MI_ALU_LOAD, MI_ALU_SRCA, MI_ALU_REG0);
+ dw[2] = mi_alu(MI_ALU_LOAD, MI_ALU_SRCB, MI_ALU_REG1);
+ dw[3] = mi_alu(MI_ALU_AND, 0, 0);
+ dw[4] = mi_alu(MI_ALU_STORE, MI_ALU_REG0, MI_ALU_ACCU);
}
/*
for (int o = 0; o < outer_count; o++) {
/* Submit one MI_MATH to shift left by 6 bits */
uint32_t *dw = anv_batch_emitn(batch, cmd_len, GENX(MI_MATH));
+ if (!dw) {
+ anv_batch_set_error(batch, VK_ERROR_OUT_OF_HOST_MEMORY);
+ return;
+ }
+
dw++;
for (int i = 0; i < inner_count; i++, dw += 4) {
- dw[0] = alu(OPCODE_LOAD, OPERAND_SRCA, OPERAND_R0);
- dw[1] = alu(OPCODE_LOAD, OPERAND_SRCB, OPERAND_R0);
- dw[2] = alu(OPCODE_ADD, 0, 0);
- dw[3] = alu(OPCODE_STORE, OPERAND_R0, OPERAND_ACCU);
+ dw[0] = mi_alu(MI_ALU_LOAD, MI_ALU_SRCA, MI_ALU_REG0);
+ dw[1] = mi_alu(MI_ALU_LOAD, MI_ALU_SRCB, MI_ALU_REG0);
+ dw[2] = mi_alu(MI_ALU_ADD, 0, 0);
+ dw[3] = mi_alu(MI_ALU_STORE, MI_ALU_REG0, MI_ALU_ACCU);
}
}
}
static void
gpu_write_query_result(struct anv_batch *batch,
- struct anv_buffer *dst_buffer, uint32_t dst_offset,
+ struct anv_address dst_addr,
VkQueryResultFlags flags,
uint32_t value_index, uint32_t reg)
{
- if (flags & VK_QUERY_RESULT_64_BIT)
- dst_offset += value_index * 8;
- else
- dst_offset += value_index * 4;
-
- anv_batch_emit(batch, GENX(MI_STORE_REGISTER_MEM), srm) {
- srm.RegisterAddress = reg;
- srm.MemoryAddress = (struct anv_address) {
- .bo = dst_buffer->bo,
- .offset = dst_buffer->offset + dst_offset,
- };
- }
-
if (flags & VK_QUERY_RESULT_64_BIT) {
- anv_batch_emit(batch, GENX(MI_STORE_REGISTER_MEM), srm) {
- srm.RegisterAddress = reg + 4;
- srm.MemoryAddress = (struct anv_address) {
- .bo = dst_buffer->bo,
- .offset = dst_buffer->offset + dst_offset + 4,
- };
- }
+ emit_srm64(batch, anv_address_add(dst_addr, value_index * 8), reg);
+ } else {
+ emit_srm32(batch, anv_address_add(dst_addr, value_index * 4), reg);
}
}
static void
compute_query_result(struct anv_batch *batch, uint32_t dst_reg,
- struct anv_bo *bo, uint32_t offset)
+ struct anv_address addr)
{
- emit_load_alu_reg_u64(batch, CS_GPR(0), bo, offset);
- emit_load_alu_reg_u64(batch, CS_GPR(1), bo, offset + 8);
+ emit_load_alu_reg_u64(batch, CS_GPR(0), anv_address_add(addr, 0));
+ emit_load_alu_reg_u64(batch, CS_GPR(1), anv_address_add(addr, 8));
/* FIXME: We need to clamp the result for 32 bit. */
return;
}
- dw[1] = alu(OPCODE_LOAD, OPERAND_SRCA, OPERAND_R1);
- dw[2] = alu(OPCODE_LOAD, OPERAND_SRCB, OPERAND_R0);
- dw[3] = alu(OPCODE_SUB, 0, 0);
- dw[4] = alu(OPCODE_STORE, dst_reg, OPERAND_ACCU);
+ dw[1] = mi_alu(MI_ALU_LOAD, MI_ALU_SRCA, MI_ALU_REG1);
+ dw[2] = mi_alu(MI_ALU_LOAD, MI_ALU_SRCB, MI_ALU_REG0);
+ dw[3] = mi_alu(MI_ALU_SUB, 0, 0);
+ dw[4] = mi_alu(MI_ALU_STORE, dst_reg, MI_ALU_ACCU);
}
void genX(CmdCopyQueryPoolResults)(
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
ANV_FROM_HANDLE(anv_query_pool, pool, queryPool);
ANV_FROM_HANDLE(anv_buffer, buffer, destBuffer);
- uint32_t slot_offset;
if (flags & VK_QUERY_RESULT_WAIT_BIT) {
anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
}
}
+ struct anv_address dest_addr = anv_address_add(buffer->address, destOffset);
for (uint32_t i = 0; i < queryCount; i++) {
- slot_offset = (firstQuery + i) * pool->stride;
+ struct anv_address query_addr = anv_query_address(pool, firstQuery + i);
+ uint32_t idx = 0;
switch (pool->type) {
case VK_QUERY_TYPE_OCCLUSION:
- compute_query_result(&cmd_buffer->batch, OPERAND_R2,
- &pool->bo, slot_offset + 8);
- gpu_write_query_result(&cmd_buffer->batch, buffer, destOffset,
- flags, 0, CS_GPR(2));
+ compute_query_result(&cmd_buffer->batch, MI_ALU_REG2,
+ anv_address_add(query_addr, 8));
+ gpu_write_query_result(&cmd_buffer->batch, dest_addr,
+ flags, idx++, CS_GPR(2));
break;
case VK_QUERY_TYPE_PIPELINE_STATISTICS: {
uint32_t statistics = pool->pipeline_statistics;
- uint32_t idx = 0;
while (statistics) {
uint32_t stat = u_bit_scan(&statistics);
- compute_query_result(&cmd_buffer->batch, OPERAND_R0,
- &pool->bo, slot_offset + idx * 16 + 8);
+ compute_query_result(&cmd_buffer->batch, MI_ALU_REG0,
+ anv_address_add(query_addr, idx * 16 + 8));
/* WaDividePSInvocationCountBy4:HSW,BDW */
if ((cmd_buffer->device->info.gen == 8 ||
shr_gpr0_by_2_bits(&cmd_buffer->batch);
}
- gpu_write_query_result(&cmd_buffer->batch, buffer, destOffset,
- flags, idx, CS_GPR(0));
-
- idx++;
+ gpu_write_query_result(&cmd_buffer->batch, dest_addr,
+ flags, idx++, CS_GPR(0));
}
- assert(idx == _mesa_bitcount(pool->pipeline_statistics));
+ assert(idx == util_bitcount(pool->pipeline_statistics));
break;
}
case VK_QUERY_TYPE_TIMESTAMP:
emit_load_alu_reg_u64(&cmd_buffer->batch,
- CS_GPR(2), &pool->bo, slot_offset + 8);
- gpu_write_query_result(&cmd_buffer->batch, buffer, destOffset,
+ CS_GPR(2), anv_address_add(query_addr, 8));
+ gpu_write_query_result(&cmd_buffer->batch, dest_addr,
flags, 0, CS_GPR(2));
break;
}
if (flags & VK_QUERY_RESULT_WITH_AVAILABILITY_BIT) {
- uint32_t idx = (pool->type == VK_QUERY_TYPE_PIPELINE_STATISTICS) ?
- _mesa_bitcount(pool->pipeline_statistics) : 1;
-
- emit_load_alu_reg_u64(&cmd_buffer->batch, CS_GPR(0),
- &pool->bo, slot_offset);
- gpu_write_query_result(&cmd_buffer->batch, buffer, destOffset,
+ emit_load_alu_reg_u64(&cmd_buffer->batch, CS_GPR(0), query_addr);
+ gpu_write_query_result(&cmd_buffer->batch, dest_addr,
flags, idx, CS_GPR(0));
}
- destOffset += destStride;
+ dest_addr = anv_address_add(dest_addr, destStride);
}
}
projects / mesa.git / blobdiff