vulkan/util: add struct vk_pipeline_cache_header

[mesa.git] / src / intel / vulkan / genX_state.c

diff --git a/src/intel/vulkan/genX_state.c b/src/intel/vulkan/genX_state.c
index 316a56ab73068ecdb4d89d3fac105e94358a4cbd..908c676a880550702c494772d3eda5be918e9ecc 100644 (file)
--- a/src/intel/vulkan/genX_state.c
+++ b/src/intel/vulkan/genX_state.c
@@ -256,15 +256,17 @@ genX(init_device_state)(struct anv_device *device)
 #endif
 
 #if GEN_GEN == 12
-   uint64_t aux_base_addr = gen_aux_map_get_base(device->aux_map_ctx);
-   assert(aux_base_addr % (32 * 1024) == 0);
-   anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
-      lri.RegisterOffset = GENX(GFX_AUX_TABLE_BASE_ADDR_num);
-      lri.DataDWord = aux_base_addr & 0xffffffff;
-   }
-   anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
-      lri.RegisterOffset = GENX(GFX_AUX_TABLE_BASE_ADDR_num) + 4;
-      lri.DataDWord = aux_base_addr >> 32;
+   if (device->info.has_aux_map) {
+      uint64_t aux_base_addr = gen_aux_map_get_base(device->aux_map_ctx);
+      assert(aux_base_addr % (32 * 1024) == 0);
+      anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
+         lri.RegisterOffset = GENX(GFX_AUX_TABLE_BASE_ADDR_num);
+         lri.DataDWord = aux_base_addr & 0xffffffff;
+      }
+      anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
+         lri.RegisterOffset = GENX(GFX_AUX_TABLE_BASE_ADDR_num) + 4;
+         lri.DataDWord = aux_base_addr >> 32;
+      }
    }
 #endif