ARM: Implement the SRS instruction.

[gem5.git] / src / kern / system_events.cc

diff --git a/src/kern/system_events.cc b/src/kern/system_events.cc
index fe3805ce26f27874af2ecf01dcb38a5ad390c00f..bd01ed9ede0a1834cd1fd6fb00a6115f4e4e5027 100644 (file)
--- a/src/kern/system_events.cc
+++ b/src/kern/system_events.cc
@@ -29,11 +29,11 @@
  *          Nathan Binkert
  */
 
-#include "cpu/base.hh"
+#include "arch/isa_traits.hh"
+#include "base/trace.hh"
+#include "config/the_isa.hh"
 #include "cpu/thread_context.hh"
-#include "kern/kernel_stats.hh"
 #include "kern/system_events.hh"
-#include "sim/system.hh"
 
 using namespace TheISA;
 
@@ -47,51 +47,7 @@ SkipFuncEvent::process(ThreadContext *tc)
 
     tc->setPC(newpc);
     tc->setNextPC(tc->readPC() + sizeof(TheISA::MachInst));
-/*
-    BranchPred *bp = tc->getCpuPtr()->getBranchPred();
-    if (bp != NULL) {
-        bp->popRAS(tc->getThreadNum());
-    }
-*/
-}
-
-
-FnEvent::FnEvent(PCEventQueue *q, const std::string &desc, Addr addr,
-                 Stats::MainBin *bin)
-    : PCEvent(q, desc, addr), _name(desc), mybin(bin)
-{
-}
-
-void
-FnEvent::process(ThreadContext *tc)
-{
-    if (tc->misspeculating())
-        return;
-
-    tc->getSystemPtr()->kernelBinning->call(tc, mybin);
-}
-
-void
-IdleStartEvent::process(ThreadContext *tc)
-{
-    if (tc->getKernelStats())
-        tc->getKernelStats()->setIdleProcess(
-            tc->readMiscReg(AlphaISA::IPR_PALtemp23), tc);
-    remove();
-}
-
-void
-InterruptStartEvent::process(ThreadContext *tc)
-{
-    if (tc->getKernelStats())
-        tc->getKernelStats()->mode(Kernel::interrupt, tc);
-}
-
-void
-InterruptEndEvent::process(ThreadContext *tc)
-{
-    // We go back to kernel, if we are user, inside the rti
-    // pal code we will get switched to user because of the ICM write
-    if (tc->getKernelStats())
-        tc->getKernelStats()->mode(Kernel::kernel, tc);
+#if ISA_HAS_DELAY_SLOT
+    tc->setNextPC(tc->readNextPC() + sizeof(TheISA::MachInst));
+#endif
 }