arch, cpu, dev, gpu, mem, sim, python: start using getPort.

[gem5.git] / src / learning_gem5 / part2 / simple_memobj.cc

diff --git a/src/learning_gem5/part2/simple_memobj.cc b/src/learning_gem5/part2/simple_memobj.cc
index cb4d3d8db9f0a14f9c6891332c8787d4e779981e..c9af3461f72e0910d450a1c37823d936a62959d3 100644 (file)
--- a/src/learning_gem5/part2/simple_memobj.cc
+++ b/src/learning_gem5/part2/simple_memobj.cc
@@ -41,33 +41,21 @@ SimpleMemobj::SimpleMemobj(SimpleMemobjParams *params) :
 {
 }
 
-BaseMasterPort&
-SimpleMemobj::getMasterPort(const std::string& if_name, PortID idx)
+Port &
+SimpleMemobj::getPort(const std::string &if_name, PortID idx)
 {
     panic_if(idx != InvalidPortID, "This object doesn't support vector ports");
 
     // This is the name from the Python SimObject declaration (SimpleMemobj.py)
     if (if_name == "mem_side") {
         return memPort;
-    } else {
-        // pass it along to our super class
-        return MemObject::getMasterPort(if_name, idx);
-    }
-}
-
-BaseSlavePort&
-SimpleMemobj::getSlavePort(const std::string& if_name, PortID idx)
-{
-    panic_if(idx != InvalidPortID, "This object doesn't support vector ports");
-
-    // This is the name from the Python SimObject declaration in SimpleCache.py
-    if (if_name == "inst_port") {
+    } else if (if_name == "inst_port") {
         return instPort;
     } else if (if_name == "data_port") {
         return dataPort;
     } else {
         // pass it along to our super class
-        return MemObject::getSlavePort(if_name, idx);
+        return MemObject::getPort(if_name, idx);
     }
 }