import Chisel._
import chisel3.experimental.{withClockAndReset}
+import freechips.rocketchip.util.SyncResetSynchronizerShiftReg
import sifive.blocks.devices.pinctrl.{Pin, PinCtrl}
-import sifive.blocks.util.ShiftRegisterInit
-
-
-class I2CPins[T <: Pin](pingen: () => T) extends Bundle {
+class I2CSignals[T <: Data](private val pingen: () => T) extends Bundle {
val scl: T = pingen()
val sda: T = pingen()
+}
+
+class I2CPins[T <: Pin](pingen: () => T) extends I2CSignals[T](pingen)
- override def cloneType: this.type =
- this.getClass.getConstructors.head.newInstance(pingen).asInstanceOf[this.type]
+object I2CPinsFromPort {
- def fromI2CPort(i2c: I2CPort, clock: Clock, reset: Bool, syncStages: Int = 0) = {
+ def apply[T <: Pin](pins: I2CSignals[T], i2c: I2CPort, clock: Clock, reset: Bool, syncStages: Int = 0) = {
withClockAndReset(clock, reset) {
- scl.outputPin(i2c.scl.out, pue=true.B, ie = true.B)
- scl.o.oe := i2c.scl.oe
- i2c.scl.in := ShiftRegisterInit(scl.i.ival, syncStages, Bool(true))
+ pins.scl.outputPin(i2c.scl.out, pue=true.B, ie = true.B)
+ pins.scl.o.oe := i2c.scl.oe
+ i2c.scl.in := SyncResetSynchronizerShiftReg(pins.scl.i.ival, syncStages, init = Bool(true),
+ name = Some("i2c_scl_sync"))
- sda.outputPin(i2c.sda.out, pue=true.B, ie = true.B)
- sda.o.oe := i2c.sda.oe
- i2c.sda.in := ShiftRegisterInit(sda.i.ival, syncStages, Bool(true))
+ pins.sda.outputPin(i2c.sda.out, pue=true.B, ie = true.B)
+ pins.sda.o.oe := i2c.sda.oe
+ i2c.sda.in := SyncResetSynchronizerShiftReg(pins.sda.i.ival, syncStages, init = Bool(true),
+ name = Some("i2c_sda_sync"))
}
}
}