package sifive.blocks.devices.i2c
import Chisel._
-import sifive.blocks.devices.gpio.{GPIOPin, GPIOOutputPinCtrl}
-import sifive.blocks.util.ShiftRegisterInit
+import chisel3.experimental.{withClockAndReset}
+import freechips.rocketchip.util.SyncResetSynchronizerShiftReg
+import sifive.blocks.devices.pinctrl.{Pin, PinCtrl}
+class I2CPins[T <: Pin](pingen: () => T) extends Bundle {
-class I2CPinsIO extends Bundle {
- val scl = new GPIOPin
- val sda = new GPIOPin
-}
+ val scl: T = pingen()
+ val sda: T = pingen()
-class I2CGPIOPort(syncStages: Int = 0) extends Module {
- val io = new Bundle{
- val i2c = new I2CPort().flip()
- val pins = new I2CPinsIO
- }
+ override def cloneType: this.type =
+ this.getClass.getConstructors.head.newInstance(pingen).asInstanceOf[this.type]
- GPIOOutputPinCtrl(io.pins.scl, io.i2c.scl.out, pue=true.B, ie = true.B)
- io.pins.scl.o.oe := io.i2c.scl.oe
- io.i2c.scl.in := ShiftRegisterInit(io.pins.scl.i.ival, syncStages, Bool(true))
+ def fromPort(i2c: I2CPort, clock: Clock, reset: Bool, syncStages: Int = 0) = {
+ withClockAndReset(clock, reset) {
+ scl.outputPin(i2c.scl.out, pue=true.B, ie = true.B)
+ scl.o.oe := i2c.scl.oe
+ i2c.scl.in := SyncResetSynchronizerShiftReg(scl.i.ival, syncStages, init = Bool(true),
+ name = Some("i2c_scl_sync"))
- GPIOOutputPinCtrl(io.pins.sda, io.i2c.sda.out, pue=true.B, ie = true.B)
- io.pins.sda.o.oe := io.i2c.sda.oe
- io.i2c.sda.in := ShiftRegisterInit(io.pins.sda.i.ival, syncStages, Bool(true))
+ sda.outputPin(i2c.sda.out, pue=true.B, ie = true.B)
+ sda.o.oe := i2c.sda.oe
+ i2c.sda.in := SyncResetSynchronizerShiftReg(sda.i.ival, syncStages, init = Bool(true),
+ name = Some("i2c_sda_sync"))
+ }
+ }
}