import Chisel._
import config.Field
-import diplomacy.LazyModule
-import rocketchip.{
- HasTopLevelNetworks,
- HasTopLevelNetworksBundle,
- HasTopLevelNetworksModule
-}
+import diplomacy.{LazyModule,LazyMultiIOModuleImp}
+import rocketchip.HasSystemNetworks
import uncore.tilelink2.TLFragmenter
import util.HeterogeneousBag
import sifive.blocks.devices.gpio._
-class PWMPortIO(c: PWMParams) extends Bundle {
+class PWMPortIO(val c: PWMParams) extends Bundle {
val port = Vec(c.ncmp, Bool()).asOutput
override def cloneType: this.type = new PWMPortIO(c).asInstanceOf[this.type]
}
-class PWMPinsIO(c: PWMParams) extends Bundle {
+class PWMPinsIO(val c: PWMParams) extends Bundle {
val pwm = Vec(c.ncmp, new GPIOPin)
}
-class PWMGPIOPort(c: PWMParams) extends Module {
+class PWMGPIOPort(val c: PWMParams) extends Module {
val io = new Bundle {
val pwm = new PWMPortIO(c).flip()
val pins = new PWMPinsIO(c)
case object PeripheryPWMKey extends Field[Seq[PWMParams]]
-trait HasPeripheryPWM extends HasTopLevelNetworks {
+trait HasPeripheryPWM extends HasSystemNetworks {
val pwmParams = p(PeripheryPWMKey)
val pwms = pwmParams map { params =>
val pwm = LazyModule(new TLPWM(peripheryBusBytes, params))
}
}
-trait HasPeripheryPWMBundle extends HasTopLevelNetworksBundle {
- val outer: HasPeripheryPWM
- val pwms = HeterogeneousBag(outer.pwmParams.map(new PWMPortIO(_)))
+trait HasPeripheryPWMBundle {
+ val pwms: HeterogeneousBag[PWMPortIO]
+
+ def PWMtoGPIOPins(dummy: Int = 1): Seq[PWMGPIOPort] = pwms.map { p =>
+ val pin = Module(new PWMGPIOPort(p.c))
+ pin.io.pwm <> p
+ pin
+ }
}
-trait HasPeripheryPWMModule extends HasTopLevelNetworksModule {
+trait HasPeripheryPWMModuleImp extends LazyMultiIOModuleImp with HasPeripheryPWMBundle {
val outer: HasPeripheryPWM
- val io: HasPeripheryPWMBundle
+ val pwms = IO(HeterogeneousBag(outer.pwmParams.map(new PWMPortIO(_))))
- (io.pwms zip outer.pwms) foreach { case (io, device) =>
+ (pwms zip outer.pwms) foreach { case (io, device) =>
io.port := device.module.io.gpio
}
}