import Chisel._
-class SPIInnerIO(c: SPIConfigBase) extends SPILinkIO(c) {
+class SPIInnerIO(c: SPIParamsBase) extends SPILinkIO(c) {
val lock = Bool(OUTPUT)
}
-class SPIArbiter(c: SPIConfigBase, n: Int) extends Module {
+class SPIArbiter(c: SPIParamsBase, n: Int) extends Module {
val io = new Bundle {
val inner = Vec(n, new SPIInnerIO(c)).flip
val outer = new SPILinkIO(c)
io.outer.tx.bits := Mux1H(sel, io.inner.map(_.tx.bits))
io.outer.cnt := Mux1H(sel, io.inner.map(_.cnt))
io.outer.fmt := Mux1H(sel, io.inner.map(_.fmt))
- io.outer.cs := Mux1H(sel, io.inner.map(_.cs))
+ // Workaround for overzealous combinational loop detection
+ io.outer.cs := Mux(sel(0), io.inner(0).cs, io.inner(1).cs)
+ require(n == 2, "SPIArbiter currently only supports 2 clients")
(io.inner zip sel).foreach { case (inner, s) =>
inner.tx.ready := io.outer.tx.ready && s