package sifive.blocks.devices.spi
import Chisel._
-import config.Field
-import diplomacy.LazyModule
-import rocketchip.{
- HasTopLevelNetworks,
- HasTopLevelNetworksBundle,
- HasTopLevelNetworksModule
-}
-import uncore.tilelink2.{TLFragmenter, TLWidthWidget}
-import util.HeterogeneousBag
+import freechips.rocketchip.config.Field
+import freechips.rocketchip.diplomacy.{LazyModule,LazyMultiIOModuleImp}
+import freechips.rocketchip.chip.HasSystemNetworks
+import freechips.rocketchip.tilelink.{TLFragmenter,TLWidthWidget}
+import freechips.rocketchip.util.HeterogeneousBag
case object PeripherySPIKey extends Field[Seq[SPIParams]]
-trait HasPeripherySPI extends HasTopLevelNetworks {
+trait HasPeripherySPI extends HasSystemNetworks {
val spiParams = p(PeripherySPIKey)
val spis = spiParams map { params =>
val spi = LazyModule(new TLSPI(peripheryBusBytes, params))
}
}
-trait HasPeripherySPIBundle extends HasTopLevelNetworksBundle {
- val outer: HasPeripherySPI
- val spis = HeterogeneousBag(outer.spiParams.map(new SPIPortIO(_)))
+trait HasPeripherySPIBundle {
+ val spi: HeterogeneousBag[SPIPortIO]
+
}
-trait HasPeripherySPIModule extends HasTopLevelNetworksModule {
+trait HasPeripherySPIModuleImp extends LazyMultiIOModuleImp with HasPeripherySPIBundle {
val outer: HasPeripherySPI
- val io: HasPeripherySPIBundle
- (io.spis zip outer.spis).foreach { case (io, device) =>
+ val spi = IO(HeterogeneousBag(outer.spiParams.map(new SPIPortIO(_))))
+
+ (spi zip outer.spis).foreach { case (io, device) =>
io <> device.module.io.port
}
}
-case object PeripherySPIFlashKey extends Field[SPIFlashParams]
+case object PeripherySPIFlashKey extends Field[Seq[SPIFlashParams]]
-trait HasPeripherySPIFlash extends HasTopLevelNetworks {
+trait HasPeripherySPIFlash extends HasSystemNetworks {
val spiFlashParams = p(PeripherySPIFlashKey)
- val qspi = LazyModule(new TLSPIFlash(peripheryBusBytes, spiFlashParams))
- qspi.rnode := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
- qspi.fnode := TLFragmenter(1, cacheBlockBytes)(TLWidthWidget(peripheryBusBytes)(peripheryBus.node))
- intBus.intnode := qspi.intnode
+ val qspis = spiFlashParams map { params =>
+ val qspi = LazyModule(new TLSPIFlash(peripheryBusBytes, params))
+ qspi.rnode := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
+ qspi.fnode := TLFragmenter(1, cacheBlockBytes)(TLWidthWidget(peripheryBusBytes)(peripheryBus.node))
+ intBus.intnode := qspi.intnode
+ qspi
+ }
}
-trait HasPeripherySPIFlashBundle extends HasTopLevelNetworksBundle {
- val outer: HasPeripherySPIFlash
- val qspi = new SPIPortIO(outer.spiFlashParams)
+trait HasPeripherySPIFlashBundle {
+ val qspi: HeterogeneousBag[SPIPortIO]
+
}
-trait HasPeripherySPIFlashModule extends HasTopLevelNetworksModule {
+trait HasPeripherySPIFlashModuleImp extends LazyMultiIOModuleImp with HasPeripherySPIFlashBundle {
val outer: HasPeripherySPIFlash
- val io: HasPeripherySPIFlashBundle
- io.qspi <> outer.qspi.module.io.port
+ val qspi = IO(HeterogeneousBag(outer.spiFlashParams.map(new SPIPortIO(_))))
+
+ (qspi zip outer.qspis) foreach { case (io, device) =>
+ io <> device.module.io.port
+ }
}
+