package sifive.blocks.devices.spi
import Chisel._
-import config._
-import diplomacy._
-import regmapper._
-import uncore.tilelink2._
+import freechips.rocketchip.config.Parameters
+import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.regmapper._
+import freechips.rocketchip.tilelink._
+import freechips.rocketchip.util.HeterogeneousBag
-trait SPIFlashConfigBase extends SPIConfigBase {
+trait SPIFlashParamsBase extends SPIParamsBase {
val fAddress: BigInt
val fSize: BigInt
+ val fBufferDepth: Int
val insnAddrBytes: Int
val insnPadLenBits: Int
lazy val insnAddrLenBits = log2Floor(insnAddrBytes) + 1
}
-case class SPIFlashConfig(
+case class SPIFlashParams(
rAddress: BigInt,
fAddress: BigInt,
+ fBufferDepth: Int = 0,
rSize: BigInt = 0x1000,
fSize: BigInt = 0x20000000,
rxDepth: Int = 8,
delayBits: Int = 8,
divisorBits: Int = 12,
sampleDelay: Int = 2)
- extends SPIFlashConfigBase {
+ extends SPIFlashParamsBase {
val frameBits = 8
val insnAddrBytes = 4
val insnPadLenBits = 4
require(sampleDelay >= 0)
}
-class SPIFlashTopBundle(i: Vec[Vec[Bool]], r: Vec[TLBundle], val f: Vec[TLBundle]) extends SPITopBundle(i, r)
-
-class SPIFlashTopModule[B <: SPIFlashTopBundle]
- (c: SPIFlashConfigBase, bundle: => B, outer: TLSPIFlashBase)
- extends SPITopModule(c, bundle, outer) {
+class SPIFlashTopModule(c: SPIFlashParamsBase, outer: TLSPIFlashBase)
+ extends SPITopModule(c, outer) {
val flash = Module(new SPIFlashMap(c))
val arb = Module(new SPIArbiter(c, 2))
- private val f = io.tl.f.head
+ private val (f, _) = outer.fnode.in(0)
// Tie unused channels
f.b.valid := Bool(false)
f.c.ready := Bool(true)
flash.io.addr.valid := f.a.valid
f.a.ready := flash.io.addr.ready
- f.d.bits := outer.fnode.edgesIn.head.AccessAck(a, UInt(0), flash.io.data.bits)
+ f.d.bits := outer.fnode.edges.in.head.AccessAck(a, flash.io.data.bits)
f.d.valid := flash.io.data.valid
flash.io.data.ready := f.d.ready
SPICRs.insnpad -> Seq(RegField(c.frameBits, insn.pad.code)))
}
-abstract class TLSPIFlashBase(c: SPIFlashConfigBase)(implicit p: Parameters) extends TLSPIBase(c)(p) {
+abstract class TLSPIFlashBase(w: Int, c: SPIFlashParamsBase)(implicit p: Parameters) extends TLSPIBase(w,c)(p) {
require(isPow2(c.fSize))
- val fnode = TLManagerNode(1, TLManagerParameters(
- address = Seq(AddressSet(c.fAddress, c.fSize-1)),
- regionType = RegionType.UNCACHED,
- executable = true,
- supportsGet = TransferSizes(1, 1),
- fifoId = Some(0)))
+ val fnode = TLManagerNode(Seq(TLManagerPortParameters(
+ managers = Seq(TLManagerParameters(
+ address = Seq(AddressSet(c.fAddress, c.fSize-1)),
+ resources = device.reg("mem"),
+ regionType = RegionType.UNCACHED,
+ executable = true,
+ supportsGet = TransferSizes(1, 1),
+ fifoId = Some(0))),
+ beatBytes = 1)))
}
-class TLSPIFlash(c: SPIFlashConfig)(implicit p: Parameters) extends TLSPIFlashBase(c)(p) {
- lazy val module = new SPIFlashTopModule(c,
- new SPIFlashTopBundle(intnode.bundleOut, rnode.bundleIn, fnode.bundleIn), this) {
+class TLSPIFlash(w: Int, c: SPIFlashParams)(implicit p: Parameters) extends TLSPIFlashBase(w,c)(p) {
+ lazy val module = new SPIFlashTopModule(c, this) {
arb.io.inner(0) <> flash.io.link
arb.io.inner(1) <> fifo.io.link