package sifive.blocks.devices.uart
import Chisel._
-import config._
-import diplomacy._
-import uncore.tilelink2._
-import rocketchip._
+import config.Field
+import diplomacy.{LazyModule, LazyMultiIOModuleImp}
+import rocketchip.HasSystemNetworks
+import uncore.tilelink2.TLFragmenter
import sifive.blocks.devices.gpio.{GPIOPin, GPIOOutputPinCtrl, GPIOInputPinCtrl}
import sifive.blocks.util.ShiftRegisterInit
-trait PeripheryUART {
- this: TopNetwork {
- val uartConfigs: Seq[UARTConfig]
- } =>
- val uart = uartConfigs.zipWithIndex.map { case (c, i) =>
- val uart = LazyModule(new UART(c))
- uart.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
+case object PeripheryUARTKey extends Field[Seq[UARTParams]]
+
+trait HasPeripheryUART extends HasSystemNetworks {
+ val uartParams = p(PeripheryUARTKey)
+ val uarts = uartParams map { params =>
+ val uart = LazyModule(new TLUART(peripheryBusBytes, params))
+ uart.node := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
intBus.intnode := uart.intnode
uart
}
}
-trait PeripheryUARTBundle {
- this: { val uartConfigs: Seq[UARTConfig] } =>
- val uarts = Vec(uartConfigs.size, new UARTPortIO)
+trait HasPeripheryUARTBundle {
+ val uarts: Vec[UARTPortIO]
+
+ def tieoffUARTs(dummy: Int = 1) {
+ uarts.foreach { _.rxd := UInt(1) }
+ }
+
+ def UARTtoGPIOPins(syncStages: Int = 0): Seq[UARTPinsIO] = uarts.map { u =>
+ val pins = Module(new UARTGPIOPort(syncStages))
+ pins.io.uart <> u
+ pins.io.pins
+ }
}
-trait PeripheryUARTModule {
- this: TopNetworkModule {
- val outer: PeripheryUART
- val io: PeripheryUARTBundle
- } =>
- (io.uarts zip outer.uart).foreach { case (io, device) =>
+trait HasPeripheryUARTModuleImp extends LazyMultiIOModuleImp with HasPeripheryUARTBundle {
+ val outer: HasPeripheryUART
+ val uarts = IO(Vec(outer.uartParams.size, new UARTPortIO))
+
+ (uarts zip outer.uarts).foreach { case (io, device) =>
io <> device.module.io.port
}
}