val slave = TLInputNode()
val control = TLInputNode()
val master = TLOutputNode()
- val intnode = IntSourceNode(1)
+ val intnode = IntOutputNode()
val axi_to_pcie_x1 = LazyModule(new VC707AXIToPCIeX1)
- axi_to_pcie_x1.slave := TLToAXI4(idBits=4)(slave)
- axi_to_pcie_x1.control := AXI4Fragmenter(lite=true, maxInFlight=4)(TLToAXI4(idBits=0)(control))
- master := TLWidthWidget(64)(AXI4ToTL()(AXI4Fragmenter()(axi_to_pcie_x1.master)))
+
+ axi_to_pcie_x1.slave :=
+ AXI4Buffer()(
+ AXI4UserYanker()(
+ AXI4Deinterleaver(p(coreplex.CacheBlockBytes))(
+ AXI4IdIndexer(idBits=4)(
+ TLToAXI4(beatBytes=8)(
+ slave)))))
+
+ axi_to_pcie_x1.control :=
+ AXI4Buffer()(
+ AXI4UserYanker()(
+ AXI4Fragmenter()(
+ AXI4IdIndexer(idBits=0)(
+ TLToAXI4(beatBytes=4)(
+ control)))))
+
+ master :=
+ TLWidthWidget(8)(
+ AXI4ToTL()(
+ AXI4UserYanker(capMaxFlight=Some(8))(
+ AXI4Fragmenter()(
+ AXI4IdIndexer(idBits=0)(
+ axi_to_pcie_x1.master)))))
+
+ intnode := axi_to_pcie_x1.intnode
lazy val module = new LazyModuleImp(this) {
val io = new Bundle {
}
io.port <> axi_to_pcie_x1.module.io.port
- io.interrupt(0)(0) := axi_to_pcie_x1.module.io.interrupt_out
//PCIe Reference Clock
val ibufds_gte2 = Module(new IBUFDS_GTE2)