package sifive.blocks.devices.xilinxvc707pciex1
import Chisel._
-import diplomacy.LazyModule
-import rocketchip.{
- HasTopLevelNetworks,
- HasTopLevelNetworksModule,
- HasTopLevelNetworksBundle
-}
+import diplomacy.{LazyModule, LazyMultiIOModuleImp}
+import rocketchip.HasSystemNetworks
import uncore.tilelink2._
-trait HasPeripheryXilinxVC707PCIeX1 extends HasTopLevelNetworks {
-
+trait HasPeripheryXilinxVC707PCIeX1 extends HasSystemNetworks {
val xilinxvc707pcie = LazyModule(new XilinxVC707PCIeX1)
private val intXing = LazyModule(new IntXing)
intXing.intnode := xilinxvc707pcie.intnode
}
-trait HasPeripheryXilinxVC707PCIeX1Bundle extends HasTopLevelNetworksBundle {
- val xilinxvc707pcie = new XilinxVC707PCIeX1IO
+trait HasPeripheryXilinxVC707PCIeX1Bundle {
+ val xilinxvc707pcie: XilinxVC707PCIeX1IO
+ def connectXilinxVC707PCIeX1ToPads(pads: XilinxVC707PCIeX1Pads) {
+ pads <> xilinxvc707pcie
+ }
}
-trait HasPeripheryXilinxVC707PCIeX1Module extends HasTopLevelNetworksModule {
+trait HasPeripheryXilinxVC707PCIeX1ModuleImp extends LazyMultiIOModuleImp
+ with HasPeripheryXilinxVC707PCIeX1Bundle {
val outer: HasPeripheryXilinxVC707PCIeX1
- val io: HasPeripheryXilinxVC707PCIeX1Bundle
+ val xilinxvc707pcie = IO(new XilinxVC707PCIeX1IO)
- io.xilinxvc707pcie <> outer.xilinxvc707pcie.module.io.port
+ xilinxvc707pcie <> outer.xilinxvc707pcie.module.io.port
outer.xilinxvc707pcie.module.clock := outer.xilinxvc707pcie.module.io.port.axi_aclk_out
- outer.xilinxvc707pcie.module.reset := ~io.xilinxvc707pcie.axi_aresetn
+ outer.xilinxvc707pcie.module.reset := ~xilinxvc707pcie.axi_aresetn
}