Updates to Freedom SoCs

[freedom-sifive.git] / src / main / scala / unleashed / u500vc707devkit / System.scala

diff --git a/src/main/scala/unleashed/u500vc707devkit/System.scala b/src/main/scala/unleashed/u500vc707devkit/System.scala
new file mode 100644 (file)
index 0000000..1a02d0e
--- /dev/null
+++ b/src/main/scala/unleashed/u500vc707devkit/System.scala
@@ -0,0 +1,48 @@
+// See LICENSE for license details.
+package sifive.freedom.unleashed.u500vc707devkit
+
+import Chisel._
+
+import freechips.rocketchip.config._
+import freechips.rocketchip.coreplex._
+import freechips.rocketchip.devices.debug._
+import freechips.rocketchip.devices.tilelink._
+import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.system._
+
+import sifive.blocks.devices.gpio._
+import sifive.blocks.devices.spi._
+import sifive.blocks.devices.uart._
+
+import sifive.fpgashells.devices.xilinx.xilinxvc707mig._
+import sifive.fpgashells.devices.xilinx.xilinxvc707pciex1._
+
+//-------------------------------------------------------------------------
+// U500VC707DevKitSystem
+//-------------------------------------------------------------------------
+
+class U500VC707DevKitSystem(implicit p: Parameters) extends RocketCoreplex
+    with HasPeripheryMaskROMSlave
+    with HasPeripheryDebug
+    with HasSystemErrorSlave
+    with HasPeripheryUART
+    with HasPeripherySPI
+    with HasPeripheryGPIO
+    with HasMemoryXilinxVC707MIG
+    with HasSystemXilinxVC707PCIeX1 {
+  override lazy val module = new U500VC707DevKitSystemModule(this)
+}
+
+class U500VC707DevKitSystemModule[+L <: U500VC707DevKitSystem](_outer: L)
+  extends RocketCoreplexModule(_outer)
+    with HasRTCModuleImp
+    with HasPeripheryDebugModuleImp
+    with HasPeripheryUARTModuleImp
+    with HasPeripherySPIModuleImp
+    with HasPeripheryGPIOModuleImp
+    with HasMemoryXilinxVC707MIGModuleImp
+    with HasSystemXilinxVC707PCIeX1ModuleImp {
+  // Reset vector is set to the location of the mask rom
+  val maskROMParams = p(PeripheryMaskROMKey)
+  global_reset_vector := maskROMParams(0).address.U
+}