x86: changes to apic, keyboard

[gem5.git] / src / mem / Bridge.py

diff --git a/src/mem/Bridge.py b/src/mem/Bridge.py
index 62dfb73517cb112e69c642d696f8ca0ba1173d6f..5f2cc9f40ae912fe51706913c6e6899cbb16df6e 100644 (file)
--- a/src/mem/Bridge.py
+++ b/src/mem/Bridge.py
@@ -44,6 +44,7 @@ from MemObject import MemObject
 
 class Bridge(MemObject):
     type = 'Bridge'
+    cxx_header = "mem/bridge.hh"
     slave = SlavePort('Slave port')
     master = MasterPort('Master port')
     req_size = Param.Int(16, "The number of requests to buffer")