+# Copyright (c) 2012-2013 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
# Copyright (c) 2006-2007 The Regents of The University of Michigan
# All rights reserved.
#
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Ali Saidi
+# Andreas Hansson
from m5.params import *
-from MemObject import MemObject
+from m5.objects.ClockedObject import ClockedObject
-class Bridge(MemObject):
+class Bridge(ClockedObject):
type = 'Bridge'
+ cxx_header = "mem/bridge.hh"
slave = SlavePort('Slave port')
master = MasterPort('Master port')
- req_size = Param.Int(16, "The number of requests to buffer")
- resp_size = Param.Int(16, "The number of requests to buffer")
+ req_size = Param.Unsigned(16, "The number of requests to buffer")
+ resp_size = Param.Unsigned(16, "The number of responses to buffer")
delay = Param.Latency('0ns', "The latency of this bridge")
- nack_delay = Param.Latency('0ns', "The latency of this bridge")
- write_ack = Param.Bool(False, "Should this bridge ack writes")
ranges = VectorParam.AddrRange([AllMemory],
"Address ranges to pass through the bridge")