mem-cache: Avoid write merging if there are reads in between

[gem5.git] / src / mem / Bridge.py

diff --git a/src/mem/Bridge.py b/src/mem/Bridge.py
index 5f2cc9f40ae912fe51706913c6e6899cbb16df6e..9e86c1a41a186a95b690033fac5ffe0619530671 100644 (file)
--- a/src/mem/Bridge.py
+++ b/src/mem/Bridge.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2012 ARM Limited
+# Copyright (c) 2012-2013 ARM Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -40,15 +40,15 @@
 #          Andreas Hansson
 
 from m5.params import *
-from MemObject import MemObject
+from m5.objects.ClockedObject import ClockedObject
 
-class Bridge(MemObject):
+class Bridge(ClockedObject):
     type = 'Bridge'
     cxx_header = "mem/bridge.hh"
     slave = SlavePort('Slave port')
     master = MasterPort('Master port')
-    req_size = Param.Int(16, "The number of requests to buffer")
-    resp_size = Param.Int(16, "The number of responses to buffer")
+    req_size = Param.Unsigned(16, "The number of requests to buffer")
+    resp_size = Param.Unsigned(16, "The number of responses to buffer")
     delay = Param.Latency('0ns', "The latency of this bridge")
     ranges = VectorParam.AddrRange([AllMemory],
                                    "Address ranges to pass through the bridge")